Hardware Engineer

Cisco•San Jose, CA

About The Position

The Firewall Hardware Team at Cisco is responsible for designing and developing high-performance, secure firewall hardware platforms that protect enterprise, data center, and cloud networks from evolving cyber threats. This team focuses on creating advanced hardware solutions, including FPGA-based crypto accelerators and network processing units, to deliver exceptional throughput, low latency, and robust security features.

Requirements

4+ years of experience with a Masters’ degree or 7+ years of experience with a Bachelors’ degree.
Experience in hardware design.
Experience taking complex hardware products from concept to production.
Experience with industry-standard design suites, such as Cadence Allegro/Concept, Mentor Graphics Xpedition, etc.

Nice To Haves

Deep proficiency in board design leveraging x86, ARM, and high-performance FPGA/SoC architectures.
Expert-level knowledge of high-speed interface bus design (PCIe Gen 4/5, DDR5, PAM4) and high-speed Ethernet (100G/400G).
Demonstrated expertise in designing robust power delivery networks (PDN). Proficiency in selecting and implementing DC-DC converters, LDOs, and managing power sequencing for high-current, low-voltage processors, FPGAs, and ASICs.
Advanced capability in modeling and mitigating signal integrity and power distribution challenges in dense, high-speed systems.
Strong understanding of RTL design (Verilog/System-Verilog) and its interaction with hardware/BIOS.
Exceptional ability to communicate complex technical concepts to both technical and non-technical stakeholders.

Responsibilities

Lead the hardware development lifecycle for complex, high-performance security appliances, ensuring alignment with product roadmaps and architectural standards.
Architect and drive the creation of complex circuit designs, schematics, and PCB layouts, ensuring optimal performance, signal integrity, and manufacturability.
Define and execute comprehensive design verification and validation (DVT) strategies, ensuring adherence to rigorous regulatory and performance specifications.
Serve as the primary technical authority for complex root cause analysis of hardware issues, including signal integrity, power distribution, and mechanical integration.
Act as a key technical liaison between hardware, software, BIOS, and manufacturing teams. Provide expert guidance to resolve cross-functional bottlenecks.
Drive continuous improvement in design methodologies, maintain high-quality technical documentation, and conduct rigorous design reviews to mitigate risk.
Provide technical guidance and mentorship to junior engineering staff, fostering a culture of innovation and engineering excellence.
Integrate AI-driven design, simulation, and diagnostic tools to streamline design cycles, enhance predictive quality analysis, and improve overall operational efficiency.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt employees)
flexible vacation time off program (exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)