Graduate – Analog Design Engineer

Infineon•Morrisville, NC

44d•$89,600 - $112,000•Onsite

About The Position

Infineon is seeking graduates for their Graduate Programs or first full-time roles to join their team and shape the future. This role involves designing and refining analog/mixed-signal blocks, control loops, and integrating analog blocks into chip-level designs. The position also supports silicon bring-up and requires collaboration with cross-functional teams.

Requirements

Graduating Fall 2026 or Spring 2027 with a MS or PhD in Electrical Engineering.
Hands-on experience with transistor-level analog/mixed-signal circuit design including LDOs, switching regulators, bandgap references, op-amps, or gate drivers through coursework or thesis work.
Proficiency in SPICE-based simulation tools (Cadence Spectre, HSPICE, or equivalent) with exposure to behavioral modeling using Verilog-A or MATLAB.
Familiarity with CMOS and/or BCD process technologies including high-voltage device handling, ESD/latch-up constraints, and reliability considerations (BTI, HCI, EM).
Basic understanding of analog layout techniques including device matching, parasitic extraction (PEX), and physical verification flows (DRC, LVS).
Methodical, data-driven approach to debugging with high attention to detail and the ability to correlate simulation results with silicon measurements.
Strong communicator with a collaborative mindset, capable of proactively syncing across cross-functional teams including design, test, reliability, and applications.

Responsibilities

Design and refine analog/mixed-signal blocks including op-amps, comparators, bandgaps, LDOs, charge pumps, bias generators, and ADC/DAC subcircuits at the transistor level.
Design and verify DC-DC control loops for compensation, transient response, EMI/EMC, efficiency optimization, startup/soft start, and protection features (UVLO, OCP, OVP, OTP).
Execute SPICE simulations covering DC/AC/transient analysis, stability, PSRR/CMRR, PVT corners, Monte Carlo mismatch/yield studies, and parasitic-aware post-layout verification.
Partner with layout engineers on device matching, common centroid techniques, guard rings, isolation, shielding, routing strategy, and physical verification (DRC, LVS, PEX).
Integrate analog blocks into chip-level designs with attention to biasing, I/O pad ring ESD, power domains, and startup/reset sequencing in coordination with digital/mixed-signal teams.
Support ATE/test engineering with characterization vectors and limit setting while contributing to yield ramp investigations and post-silicon correlation.
Collaborate with Systems, Applications, Reliability, Packaging, and Test/Production teams to translate system requirements into circuit specifications and ensure DfT compliance.