GPU Design Implementation Methodology Engineer

Qualcomm • San Diego, CA

7d • $141,300 - $211,900

About The Position

The Design Implementation Methodology Engineer will work on Qualcomm’s Adreno GPU Silicon team, developing and driving advanced design methodologies, infrastructure, and automation across synthesis, static timing analysis (STA), power, and physical design, using the latest AI methodologies and frameworks.

This is a hands-on role that combines methodology and infrastructure development with applying those capabilities to real design challenges. The engineer will identify opportunities for measurable improvements in process, productivity, and power, performance, and area (PPA), and work closely with synthesis, STA, physical design, power, and DFT teams to develop scalable methodologies for GPU designs. The role also includes developing agentic framework workflows for engineering analysis and automation, and driving targeted, EDA-tool-agnostic methodology and PPA improvement initiatives.

Candidates should bring a strong methodology mindset, programming and problem-solving skills, and an understanding of ASIC implementation. Candidates with exceptional technical aptitude and the ability to quickly develop implementation expertise will also be considered.

Requirements

• Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field and 2+ years of software, hardware, systems engineering, or related work experience; or a master’s degree in a listed or related field and 1+ year of such experience; or a PhD in a listed or related field.
• Strong programming and scripting skills, including Python, TCL, or similar languages.
• Working knowledge of ASIC design and implementation concepts.
• Understanding of digital design, RTL synthesis, physical design, STA, power analysis, and ASIC implementation flows.
• Experience or demonstrated ability to work across synthesis, STA, power, or physical-design domains.
• Strong analytical, problem-solving, debugging, and communication skills.
• Ability to develop scalable design infrastructure, automation, and reusable methodologies.
• Ability to apply infrastructure and analytics to improve PPA, design flows, and engineering productivity.
• Ability to work independently and collaborate across engineering teams.
• Strong self-motivation and ability to investigate and solve complex engineering problems.

Nice To Haves

• Hands-on experience with synthesis, STA, and/or physical design implementation.
• Experience with industry-standard EDA tools for synthesis, timing analysis, formal verification, power analysis, and physical design.
• Experience developing reusable TCL/Python libraries and design-analysis infrastructure.
• Experience with design-data analytics, dashboards, databases, and interfaces between design flows and data platforms.
• Experience developing methodologies for clock structure/network analysis and PPA optimization.
• Exposure to AI/LLM-based engineering applications, AI agents, or agentic workflows.
• Experience interfacing EDA tools and design infrastructure with AI/LLM systems.
• Ability to collaborate with core infrastructure and AI teams and integrate common capabilities into design methodologies.
• Strong understanding of advanced-node VLSI design and implementation challenges.

Responsibilities

• Develop and drive design methodologies, infrastructure, and automation across synthesis, STA, power, and physical design.
• Apply infrastructure and methodologies to real design challenges and identify measurable process, productivity, and PPA improvements.
• Collaborate with synthesis, STA, physical design, power, and DFT teams to develop scalable methodologies and apply them across GPU designs.
• Develop agentic framework workflows for engineering analysis and automation.
• Drive targeted, EDA-tool-agnostic synthesis, physical design, and STA methodology and PPA improvement initiatives.
• Investigate complex design problems and develop innovative methodology solutions.
• Use design data and analytics to identify actionable engineering insights and opportunities for improvement.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants, except for employees on sales-incentive plans.
• Competitive benefits package.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level