FPGA Prototyping Debug and Runtime Infrastructure Development Engineer

Siemens•Wilsonville, OR

2d•$90,000 - $162,000•Hybrid

About The Position

Siemens EDA’s FPGA Prototyping R&D team in Wilsonville develops debug and hardware-platform infrastructure for Mentor’s FPGA prototyping software system and hardware platform. The engineer contributes to the design, specification, implementation, testing, and maintenance of software and FPGA RTL hardware IP for the company’s products. The role works with a globally distributed team and includes periodic travel to R&D or customer sites when conditions allow.

Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Bachelor of Science in Computer Engineering (BSCE).
RTL design experience with SystemVerilog, Verilog, or VHDL.
Experience with ASIC and/or FPGA implementation flows, including synthesis and place and route.
Experience with Xilinx Vivado or Intel PSG Quartus flows.
Experience with RTL IP, Xilinx Vivado IP, Intel PSG Quartus IP, and design reuse.
Experience with RTL simulation, verification, debugging, and timing analysis.
Programming skills in C/C++ and Python.
Knowledge of data structures and algorithms.
Experience with Linux OS.
Self-motivated team player skilled in quality-oriented and performance-oriented software and hardware engineering.
Willingness to undertake periodic travel to R&D or customer sites.

Responsibilities

Design, implement, and maintain IP blocks in Verilog.
Validate and test designs using simulation and FPGA hardware boards.
Develop and test related software components.
Run RTL synthesis with timing and physical constraints, capacity goals, and performance goals using Xilinx Vivado and Intel PSG Quartus flows.
Analyze, debug, and tune hardware system performance.
Provide customer support to ensure smooth deployment of developed features.