Mid Level FPGA Engineer

0 Base Design LLC•Raleigh, NC

5d•$90,000 - $130,000•Hybrid

About The Position

We are seeking a skilled and motivated Mid-Level FPGA/RTL Design Engineer with a minimum of 4 to 5+ years of experience to join our engineering team in Raleigh, NC. In this role, you will own the design, implementation, and verification of digital logic targeting Xilinx and Lattice FPGA platforms, writing RTL in both Verilog and VHDL across the full development lifecycle — from architecture and simulation through synthesis, timing closure, and hardware bring-up. This position focuses heavily on producing robust, well-verified RTL and supporting the hardware/software boundary. You will balance digital design with hands-on technical execution, including lab-based debug, hardware-software integration, and system-level troubleshooting alongside embedded software engineers.

Requirements

Bachelor of Science (BS) degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
A minimum of 4 to 5+ years of professional experience writing RTL in both Verilog and VHDL, with demonstrated work on both Xilinx and Lattice FPGA platforms.
Hands-on proficiency with Vivado and Lattice Diamond/Radiant (or Lattice Propel).
Solid understanding of clock domain crossing, timing closure, synchronous/asynchronous design, FSMs, and pipelining.
Experience writing testbenches and running simulations for functional verification.
Working familiarity with embedded C/C++ sufficient to collaborate on hardware-software interfaces, debug firmware-driver issues, and support bring-up of soft-core or hard processors (e.g., MicroBlaze, Zynq PS).
Comfortable using oscilloscopes, logic analyzers, and JTAG-based tools for hardware debug.
Ability to obtain and maintain a Department of Defense (DoD) Secret Security Clearance (or equivalent agency clearance).

Nice To Haves

Experience with SERDES/transceiver design (Aurora, PCIe, MGT-based links).
Experience in Python or TCL for build automation, test automation, or tool flow scripting.
Exposure to constrained-random or formal verification methodologies (UVM, SVA).
Experience with embedded Linux bring-up, RTOS integration, or device driver development.
Familiarity with Git and CI/build pipelines for hardware projects.
Exposure to design standards applicable to defense/aerospace hardware (e.g., IPC, ISO, or military standards).
Working knowledge of signal integrity and PCB-level considerations affecting FPGA I/O.

Responsibilities

RTL Design & Implementation: Design and implement digital logic in Verilog and VHDL for FPGA-based systems, targeting Xilinx (e.g., Artix, Kintex, Zynq/Zynq UltraScale+, Versal) and Lattice (e.g., ECP5, CrossLink, Nexus/CertusPro) device families.
Verification: Develop testbenches and perform functional simulation (Vivado Simulator, CocoTB, or similar) to validate design correctness prior to hardware bring-up.
Synthesis & Timing Closure: Drive designs through synthesis, place-and-route, and timing closure using Vivado and Lattice Diamond/Radiant toolchains.
Hardware/Software Integration: Collaborate closely with embedded software engineers to define and validate hardware-software interfaces (register maps, DMA, interrupts, memory-mapped peripherals) and support firmware bring-up on FPGA-hosted processors.
Hardware Bring-up & Debug: Lead lab-based debug using ILAs, logic analyzers, oscilloscopes, and JTAG tools; troubleshoot systemic issues crossing the hardware/firmware boundary.
Interface & Requirements Support: Interface RTL with high-speed peripherals (DDR, SPI, I2C, UART, Ethernet, PCIe, SERDES/transceivers) and support Interface Control Documents (ICDs) where FPGA I/O touches other subsystems.
Documentation & Reviews: Participate in design reviews and produce clear documentation (design specs, verification plans, timing/constraint reports).
Design Methodology: Contribute to improving internal RTL design methodology, IP reuse, and verification practices.