FPGA Engineer, Amazon Leo Government

Amazon • Los Angeles, CA

2d • $136,000 - $184,000 • Onsite

About The Position

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As an FPGA engineer on the Leo Government Solutions team you will create FPGA solutions to support Amazon Project Kuiper’s satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. You will work with systems and algorithm teams to define/develop/implement/test/release FPGA-based solutions to enable Project Kuiper. In particular, your work will power high-speed communication links while making use of the latest generations of FPGA technologies, design processes, and tools. You will tackle challenging, novel situations every day and have the opportunity to work with multiple technical teams at Amazon in different locations, partner teams, and end customers.

Requirements

• Bachelor's degree in Electrical Engineering or a related field
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
• 5+ years of experience developing FPGA RTL code in System Verilog / VHDL.
• Proficiency in Verilog, SystemVerilog, or VHDL; experience with Xilinx Vivado or Microchip Libero; proficiency in Linux, scripting (Python/Perl), and interface protocols like PCIe or DDR.
• U.S. Citizen

Nice To Haves

• Master's degree in Electrical or Communications Engineering or a related field
• Experience with formal verification techniques including abstraction and end-to-end checking
• Experience with ARM and various DSP ISAs

Responsibilities

• Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure–Simulation Validation– Lab Based Silicon Validation.
• Collaborate with RF and Optical Communications and Signal Processing system architects and design engineers to define, design, implement, and test modem and digital logic functions in FPGA technology.
• Writing RTL code, developing testbenches, performing simulation and timing closure, and debugging in a laboratory environment.
• Collaborate with system architects and design engineers to implement digital logic functions in FPGA prototypes to validate/tradeoff architecture & design alternatives.
• Collaborate with systems architects, HW engineering design teams & FW/SW design teams to bring up and test systems combining FPGA gateware, Firmware, and Networking functions.
• Drive trade-off analysis to benefit customer experience and optimization of target technology resources for cost/size/power/performance/features
• Utilize FPGA design tools including Vivado / Vitis with new System Verilog / VHDL RTL code and existing/new IP core integration.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave
• sign-on payments
• restricted stock units (RSUs)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior