FPGA ENGINEER II

RTX•McKinney, TX

2d•$68,900 - $131,100•Onsite

About The Position

Raytheon’s Multi-Product Power & Digital department designs FPGAs, circuit cards, and electronics subassemblies for products including missiles/effectors, radars, and electronic warfare systems. The team applies digital, analog, and power design skills throughout the product lifecycle, from architecture and design through production and sustainment. The FPGA Engineer II provides full lifecycle support for production-quality FPGA designs using devices from one or more major vendors, including AMD (Xilinx), Altera, and Microchip (Microsemi). The role develops FPGA designs for applications such as gigabit serial interfaces, RF DSP, controls, data links, embedded processing, and processor interfaces. It contributes to system architecture, verification, documentation, and execution tracking, and operates as an individual contributor while presenting work to leadership and pursuing professional development. This is an onsite position in McKinney, Texas. U.S. citizenship and an active, existing DoD Secret clearance are required after the first day; the ability to obtain and maintain a U.S. government-issued clearance is required.

Requirements

Typically requires a STEM degree and a minimum of 2 years of prior relevant experience.
Experience in one or more of: FPGA/ASIC design using VHDL and/or Verilog, or FPGA/ASIC verification using SystemVerilog.
Experience with AMD (Xilinx), Altera, and/or Microchip (Microsemi) devices and tools such as AMD Vivado, Altera Quartus Prime Pro, or Libero.
Hands-on experience integrating and debugging FPGA/ASIC designs in a lab environment.
Experience with source code management, design reviews, and code release in a team development environment.
U.S. citizenship; only U.S. citizens are eligible for the required security clearance.
An active and existing DoD Secret clearance is required after day one, and the ability to obtain and maintain a U.S. government-issued security clearance is required.

Nice To Haves

One or more advanced degrees in Electrical Engineering or a related STEM major; a suitable degree may be counted as 2 years of work experience.
FPGA/ASIC design experience with embedded systems using ARM, MicroBlaze, or NIOS processors.
Experience with gigabit serial interfaces and multi-gigabit transceivers (MGTs).
Experience with constrained-random verification in UVM using SystemVerilog.
Experience with High Level Synthesis (HLS).
Experience with vector processors and/or GPUs.
Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
Demonstrated ability to lead design efforts and/or small teams.

Responsibilities

Provide full lifecycle support for production-quality FPGA designs for one or more major vendors and device families, including AMD (Xilinx), Altera, and Microchip (Microsemi).
Generate FPGA designs for gigabit serial interfaces, RF DSP, controls, data links, embedded processing, and processor interfaces.
Assist with architecture development for FPGA-based systems, including determining parts, interfaces, and Concept of Operations (CONOPS).
Design and code in VHDL for reliability and maintainability.
Support design verification using self-checking techniques, directed and constrained-random tests, and functional and code coverage tracking.
Understand and report execution status against planned budget and schedule using an agile framework.
Create complete documentation, including requirements, verification plans, and user guides.
Function as an individual contributor and clearly present work products to leadership.
Engage in professional growth and development.

Benefits

Medical insurance
Dental insurance
Vision insurance
Life insurance
Short-term disability
Long-term disability
401(k) match
Flexible spending accounts
Flexible work schedules
Employee assistance program
Employee Scholar Program
Parental leave
Paid time off
Holidays
Potential annual short-term and/or long-term incentive compensation, depending on position level and collective-bargaining coverage
Relocation based on candidate eligibility