FPGA Digital Engineer - 2

Northrop Grumman • Chandler, AZ

2d • $87,200 - $130,800

About The Position

Northrop Grumman Space Systems is seeking an FPGA Digital Engineer to support the Electro-Optics (EO) Group within the Launch Vehicles business unit in Chandler, Arizona. The engineer will collaborate with experienced FPGA engineers and cross-disciplinary hardware, algorithms, and software teams to support FPGA design, verification, and integration for advanced systems. This early-career role emphasizes learning and developing foundational skills while contributing to project deliverables under guidance.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline from an accredited university and 2 years of relevant experience, or a Master’s degree.
• Ability to obtain a U.S. Government Department of Defense Secret security clearance at the time of application.
• Internship, co-op, or academic project experience with FPGAs, SoCs, or digital hardware; VHDL preferred, or Verilog.
• Exposure to AMD Xilinx FPGAs and SoCs through academic or project experience.
• Familiarity with managing design constraints, including timing, power, and I/O, and using development tools such as Vivado IDE.
• Exposure to developing, verifying, or debugging digital interfaces or buses such as Ethernet, PCIe, AXI4, UART, or SDLC through coursework or projects.
• Familiarity with simulation tools such as Questa or ModelSim, or basic hardware debugging tools such as logic analyzers and oscilloscopes.
• Experience developing or running verification plans using simulation, analysis, or hardware bench testing through coursework or internships.

Nice To Haves

• Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Active U.S. Government Department of Defense Secret security clearance at the time of application.
• Direct experience with missile systems, seeker systems, or other high-reliability, environmentally challenging electro-optical applications through academic or internship experience.
• Familiarity with AMD Xilinx Versal FPGAs or SoCs.
• Exposure to Vitis Unified IDE and DDR3, DDR4, or DDR5 memory interface standards.
• Coursework or project experience with embedded C/C++ programming.
• Understanding of OSVVM or UVM verification methodologies.
• Interest in high-speed PCB design and signal integrity.

Responsibilities

• Assist senior FPGA engineers and multidisciplinary teams, under supervision, in resolving design and integration challenges.
• Participate in developing and executing test benches to verify FPGA functional and timing requirements.
• Support the generation, verification, and integration of I/O and image-processing HDL modules, including function definitions, HDL coding, module-level simulation, and integration with the overall device architecture.
• Prepare, organize, and maintain design documentation, including schematics, simulation results, and verification reports, with oversight.
• Support configuration management of FPGA bitstream builds as directed.
• Contribute to compliance with internal design standards throughout the development lifecycle.
• Continue developing technical knowledge of FPGA technologies, tools, and industry methodologies.

Benefits

• Health insurance coverage
• Life insurance
• Disability insurance
• Savings plan
• Company-paid holidays
• Paid time off (PTO) for vacation and/or personal business
• Potential eligibility for overtime, shift differential, and a discretionary bonus, depending on the position

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level