Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)

Fairwinds Technologies•Aberdeen Proving Ground, MD

16d•$150,000 - $175,000•Hybrid

About The Position

Fairwinds Technologies is seeking an FPGA Design Engineer to develop programmable logic solutions using Xilinx Vivado, Verilog, and VHDL for Xilinx Zynq UltraScale+ RFSoC, MPSoC, and Versal platforms. The role involves designing, implementing, and validating FPGA-based signal processing, RF data paths, and high-speed data movement architectures, including translating DSP engineers’ algorithms into FPGA fabric designs and integrating high-speed data converters. The engineer will collaborate with DSP, hardware, RF, embedded software, and Linux teams to deliver mission-critical communications and signal-processing systems for military and border-protection applications. The position focuses on programmable logic development, including RTL design, simulation, synthesis, timing closure, and hardware validation on PCB-based platforms. It reports to the Chief Technology & Strategy Office and includes collaboration with customers and engineering teams. The role is primarily performed in a traditional office environment, with some remote or hybrid work possible. This is a full-time, exempt position, Monday through Friday, 40 hours per week. Occasional evening and weekend work may be required, and some flexibility in actual work hours may be offered. Travel of 25–30% may be required.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in FPGA design and development.
Strong proficiency in Verilog and/or VHDL.
Deep experience with RTL simulation tools such as Siemens Questa and Vivado Simulator.
Hands-on experience with Xilinx Vivado for synthesis, implementation, timing closure, and debugging.
Hands-on experience with Xilinx Zynq UltraScale+ RFSoC.
Experience developing FPGA designs for PCB-based embedded systems.
Experience implementing DSP designs provided by DSP engineers and translating algorithm specifications into efficient RTL.
Strong understanding of AXI protocols, clock domain crossing (CDC), resets, and timing constraints.
Experience with FPGA debug tools such as ILA, VIO, and JTAG-based debugging.
U.S. citizenship and an active DoD Secret (or higher) security clearance, or ability to obtain one.
Experience integrating FPGA designs with high-speed data converters from Analog Devices or Texas Instruments AFE/ADC products.
Experience designing multi-sample-per-clock architectures for high-throughput signal processing.
Fundamental understanding of RF signal-processing concepts, including sampling theory, digital mixing, filtering, and frequency conversion.
Must be eligible to work in the United States and possess or obtain a Secret-level clearance.
Must be willing to travel 25–30% when required.

Nice To Haves

Experience with Versal devices and other devices within the UltraScale+ family.
Experience with Versal ACAP architecture, including heterogeneous compute resources such as PL, AI Engines, and hardened blocks.
Experience implementing or integrating high-speed interfaces such as JESD204B/C, Ethernet, PCIe, or Aurora in RF data-converter applications.
Strong understanding of DSP concepts and fixed-point/floating-point implementation tradeoffs in FPGA designs.
Familiarity with FPGA power optimization and performance-tuning techniques.
Tcl and/or Python scripting experience for build automation, constraints generation, and CI workflows.
Experience supporting DoD SBIR projects or similar government-funded R&D efforts.
Experience with Xilinx RFSoC integrated RF data converters and RF Data Converter IP.
Familiarity with Analog Devices reference designs and evaluation platforms, such as ADRV9009-ZU11EG.

Responsibilities

Design, implement, and verify FPGA logic using Verilog and VHDL in Xilinx Vivado for Zynq UltraScale+ RFSoC, MPSoC, and Versal devices.
Develop programmable logic architectures for signal processing, control, and high-speed data movement.
Implement DSP algorithms in FPGA fabric, including filters, FFTs, channelizers, modulators, demodulators, decimation/interpolation, and fixed-point optimization.
Work with embedded software engineers to define and implement PL–PS interfaces, including AXI-Lite, AXI-Stream, DMA, interrupts, and register maps.
Integrate FPGA designs with embedded processors and heterogeneous compute architectures.
Perform functional simulation, static timing analysis, and resource optimization to meet performance, latency, and power constraints.
Support FPGA bring-up and debugging on custom PCB hardware using JTAG, ILA, logic analyzers, and oscilloscopes.
Participate in system integration and debugging across FPGA logic, embedded software, DSP algorithms, and hardware.
Develop test benches, validation strategies, and design documentation, including FPGA design descriptions, interface control documents, and SBIR deliverables as required.
Support prototype-to-production transitions, including ECOs, version control, and configuration management.
Design and integrate interfaces with high-speed Analog Devices and Texas Instruments data converters, including JESD204B/C and LVDS interfaces.
Develop multi-sample-per-clock architectures for wideband RF signal-processing throughput requirements.
Apply fundamental RF signal-processing knowledge to digital front-end design, including NCOs, mixers, digital up/down conversion, and gain control.
Collaborate with customers and engineering teams on RF tactical and naval military solutions and strategic border-protection applications.
May mentor junior engineers and support cross-functional technical leadership.