FPGA Design Engineer

University of Southern California • Arlington, VA

6d • Hybrid

About The Position

The FPGA Design Engineer will work with the Reconfigurable Computing Group at USC’s Information Sciences Institute (ISI), which develops computer architectures and design methods to make specialized hardware more adaptable, efficient, and trustworthy. The group combines FPGA prototyping, ASIC design, electronic design automation (EDA) tools, and hardware-software co-design across research areas including RF sensing and communications, fully homomorphic encryption acceleration, and hardware security and assurance.

Working alongside senior research staff, the engineer will develop specialized FPGA designs to assess device functionality and state, conduct measurements and analyses using FPGA hardware and laboratory instrumentation, augment commercial EDA tools, and advance open-source EDA software with new assurance capabilities. The position is based in Arlington, Virginia, with hybrid work options available.

The position requires a master’s degree in a relevant field or equivalent combined education and experience, and five years of relevant experience. Candidates must be willing and eligible to apply for and maintain a Top Secret security clearance; eligibility requires U.S. citizenship. The stated annual base salary range is $115,000 to $140,000.

Requirements

• Master’s degree in computer engineering, electrical engineering, computer science, or a closely related field, or equivalent combined education and experience.
• Five years of relevant experience.
• Proficiency in RTL design using VHDL or Verilog.
• Proficiency with scripting languages such as Python or TCL.
• Proficiency with FPGA EDA tools such as AMD Xilinx Vivado or Intel Altera Quartus, including synthesis, implementation, and timing closure.
• Experience interfacing directly with FPGA hardware, power supplies, and other test instrumentation.
• Willingness and eligibility to apply for and maintain a Top Secret security clearance; U.S. citizenship is required for clearance eligibility.
• Knowledge of one or more relevant programming languages, such as Python, C++, or Golang.
• Experience with Linux, Virtual LAN and/or Virtual Extensible LAN, Mellanox switches, SDN programming, Ansible, Bash, Nagios, Prometheus, SNMP, applicable IT protocols, iptables, and Network File System.

Nice To Haves

• Seven or more years of relevant experience.
• Current Secret security clearance or higher.
• Experience applying large language model-assisted design to FPGAs or implementing AI or machine-learning workloads on FPGAs using AMD Vitis AI or Intel Altera FPGA AI Suite.
• Knowledge of FPGA architecture and device primitives, including AMD Xilinx Zynq, Virtex-7, UltraScale+, or Versal devices, or comparable Intel Altera devices.
• Contributions to or experience with open-source EDA tools such as Google Project X-Ray, VTR or VPR, RapidSmith, or TORC.
• Demonstrated use of revision-control systems such as Git or Mercurial in a multi-user project environment.
• Proven leadership ability.
• Experience in a university environment.
• Experience with artificial intelligence, VLSI design, machine learning, deep learning (such as TensorFlow, PyTorch, or HuggingFace), and Dockerization.

Responsibilities

• Design, implement, and verify specialized FPGA systems and RTL components in VHDL or Verilog for hardware-assurance research.
• Use FPGA EDA tools for synthesis, implementation, timing analysis, timing closure, and device programming.
• Interface with FPGA hardware, power supplies, and other test instrumentation to collect measurements, validate behavior, and analyze device functionality and characteristics.
• Develop Python, TCL, and related scripts to automate design flows, testing, data collection, and analysis.
• Extend commercial and open-source EDA tools to implement and evaluate FPGA-assurance capabilities.
• Collaborate with senior researchers to translate research concepts and project goals into prototypes and independently developed system components.
• Document designs, methods, test results, and technical progress; contribute to sponsor reports, publications, presentations, and collaborator meetings.
• Review technical implementations, share engineering best practices, and provide guidance or informal mentorship to junior team members as needed.
• Stay current with FPGA architectures, EDA methods, hardware-assurance research, and emerging AI-assisted design approaches relevant to project goals.

Benefits

• Comprehensive benefits, including medical coverage and matched retirement contributions.
• Opportunities for top-tier university education for the employee and their children.
• Workplace support for quality work-life balance.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior