FPGA Design Engineer

Arista Networks • Nashua, NH

6d • Onsite

About The Position

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscaler data centers, and bleeding-edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. As a core member of the FPGA Design and Verification team, you will drive the development of high-performance control path FPGAs powering Arista’s flagship data center platforms. You will own the full design lifecycle—from gathering architectural requirements and reviewing board schematics to executing rigorous verification, leading system bring-up, and supporting production deployment.

Requirements

• 5 years or more of hands-on experience in Verilog/SystemVerilog RTL design.
• Proven background in Control Path design.
• Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI).
• Local to the area

Nice To Haves

• Experience with Ethernet Data Path architecture and design.
• Hands-on experience with Streaming Bus interfaces (e.g., AXI-Stream).
• Background in FPGA resource management and timing closure.
• Proficiency in Python, Tcl, or general scripting for EDA tool automation.
• Lab Debugging & Validation: Utilize logic analyzers (LA), oscilloscopes, and vendor-specific debug tools for lab bring up, debug, and validation.

Responsibilities

• Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
• Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
• Collaborate directly with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms.
• Actively participate in peer RTL code reviews, as well as PCB schematic and board design reviews.
• Develop AI-skills, Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed