FPGA Design Engineer (Timing)

Advanced Micro Devices, Inc•San Jose, CA

4d•Hybrid

About The Position

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. As a FPGA Design Engineer, you will work with digital timing experts, FPGA circuit designers and FPGA software modeling experts to create timing model for the entire FPGA, that will be used by the FPGA toolset to ensure proper timing for the user created designs.

Requirements

Passion for digital design, and associated timings based on various operating conditions (PVT) to ensure correct functionality of a complex design.
Team player who has excellent communication skills.
Strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Bachelors or Masters degree in Electrical Engineering, Computer Engineering or equivalent.

Nice To Haves

Good understanding of digital design concepts with emphasis towards timing.
Good understanding of transistor and gate level circuit behavior.
Experience with design creation using AMD FPGA toolset is a plus.
Experience or familiarity with simulation and timing tools like VCS, PrimeTime and SPICE.
Good working knowledge in writing scripts using Python or Perl.
Experience in Silicon characterization is a plus.

Responsibilities

Run simulation on various sections of FPGA components and derive the timing information from there and pair it with the corresponding FPGA timing model.
Analyze timing numbers for the correctness and ensure no unrealistic timing numbers got generated due to any simulation setup issue.
Create special type of designs for FPGA and run them on FPGA silicon to correlate the simulated numbers with the measured timing numbers on the silicon.
Create and modify Perl and Python based scripts to automate the timing capture and analysis process.