FPGA Design Engineer Lead

Lockheed Martin•Orlando, FL

22h•Hybrid

About The Position

You will be the FPGA Design Engineer Lead for the Programmable Logic Design organization within Missiles & Fire Control (MFC). Our team defines the digital backbone of precision engagement aerospace and defense systems for the United States and allied militaries, delivering high performance FPGA/ASIC solutions that meet rigorous aerospace standards. As the FPGA Design Engineer Lead you will act as the recognized technical authority for FPGA and ASIC development across the MFC portfolio. You’ll translate system requirements into production ready architectures, mentor engineers, and steer the strategic direction of programmable logic capabilities.

Requirements

Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree or PhD preferred
Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog
Experience with multiple FPGA vendors (Xilinx/AMD, Altera/Intel, MicroSemi/Microchip) and their part families, internal fabric, and IP
Experience with FPGA simulation tools such as Synopsys VCS and verification methodologies (UVM)
Experience with version control systems such as Git/GitLab
Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance

Nice To Haves

Experience with Xilinx/AMD FPGAs (including Versal) and related toolsets (Vivado, Vitis, Vitis HLS)
Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity
Experience in hardware-software integration and validation
Experience with high-speed data and memory interface implementation
LM/MFC design experience and missile/sensor program experience
Experience with the MFC Design Assurance / DAR process
Experience with safety boards and range safety requirements (RCC 319, MIL-STD-1316, JOTP-051, MIL-STD-1901)
Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets
Experience with Simulink and HDL Coder for model-based FPGA design
Experience with EOIR imaging processing techniques and missile/processor interfaces
Proven ability to collaborate effectively with cross-functional software, hardware, and systems engineering teams
Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)

Responsibilities

Owning end to end development of sophisticated FPGA/ASIC architectures—from capture of requirements through production release.
Defining, designing, verifying, and implementing logic using VHDL/Verilog in AMD Vivado, Intel Quartus, or equivalent toolchains.
Conducting trade studies to select optimal devices, balancing logic utilization, power, thermal performance, cost, and risk.
Creating detailed requirements and interface control documents that guide cross functional teams.
Building high coverage verification environments with UVM (or comparable frameworks) and generating comprehensive test plans.
Supporting Design Assurance Reviews and ensuring compliance with MFC engineering standards and aerospace design practices.
Providing technical leadership, code review guidance, and mentorship to junior and peer engineers.
Driving the Design Architecture Development process, managing schedule milestones and mitigating technical risks.
Managing configuration control and versioning in LM approved repositories (GitLab, etc.) and maintaining complete, traceable design documentation.
Representing FPGA/ASIC engineering in cross functional technical meetings, risk assessments, schedule reviews, and customer facing engagements.