Foundry Technology Engineer

Cisco•Maynard, MA

4d•$154,900 - $225,300

About The Position

We are seeking an accomplished Engineer to join Cisco’s Component Quality and Technology team (CQT), driving the development and integration of next-generation Silicon Photonics (SiPh) and Electronic Integrated Circuits (EICs). In this role, you will serve as the technical interface between Cisco engineering and high-volume manufacturing (HVM) foundries, owning end-to-end process integration and qualification. You will translate design intent into manufacturable, reliable, and testable solutions that power the future of global networking.

Requirements

PhD or MS in Electrical Engineering, Optics, Photonics, or a related field.
4+ years of validated experience in chip development, foundry engagement, and process qualification, with demonstrated success in high-volume production environments.
Direct experience working with external foundries (e.g., TSMC, GlobalFoundries, Tower, or comparable SiPh foundries) on process bring-up is highly desired.
Knowledge in the design-for-manufacturing (DFM), design-for-reliability (DFR), and design-for-test (DFT) principles applied to the fabrication, integration, and characterization of PIC and EIC devices, across the full device lifecycle from early-stage design review through sustained HVM.
Proficient in IC design tools including Cadence Virtuoso, Synopsys, and Klayout.

Nice To Haves

Hands-on experience with hybrid bonding and thin-wafer processing
Familiarity or hands-on experience with near-package optics (NPO) or co-packaged optics (CPO) architectures is a plus.
Proven ability to work in cross-functional technical teams and lead vendor/foundry relationships
Demonstrated ability to contribute to and lead projects within matrixed, geographically distributed technical teams.

Responsibilities

Manage the end-to-end PIC and EIC tape-out lifecycle — from PDK engagement through DRC sign-off, process integration, and process qualification.
Drive bring-up of electronic-photonic integration technology platforms in partnership with internal design and external foundry teams.
Develop, modify, and optimize photonic and electronic process flows across SiPh and CMOS platforms by leveraging CMOS fabrication capabilities.
Conceptualize and execute critical process modules with a strong emphasis on design-for-manufacturing (DFM) principles, ensuring robust process windows and high yield from initial integration through HVM ramp.
Lead and optimize wafer-scale processes for advanced EIC-PIC integration using Wafer-to-Wafer and Die-to-Wafer methods, focusing on co-design and co-fabrication strategies.
Execute root-cause analysis and Design of Experiments (DOE) to address failure mechanisms in discrete and integrated components.
Apply design-for-reliability (DFR) frameworks to anticipate and eliminate failure modes early in the development cycle, and drive process qualification.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)