Fellow - FPGA architecture

Advanced Micro Devices, Inc•San Jose, CA

11d

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. We are seeking a Fellow Architect to define and drive next‑generation architecture for AMD’s adaptive FPGA devices. This role will own the architecture for FPGA configuration, readback, and Partial Reconfiguration (PR), enabling scalable, secure, and flexible deployment of programmable logic in heterogeneous SoC and chiplet environments. As a senior technical leader, you will shape the long‑term vision for bitstream architecture, configuration flows, runtime reconfiguration, debug observability, and system integration, translating customer requirements across Emulation & Prototyping, AI, Data Center, Embedded, and Automotive into differentiated FPGA capabilities. You will collaborate across silicon, RTL, tools, software, and customer teams.

Requirements

Recognized expert in FPGA architecture with deep expertise of Configuration and Partial Reconfiguration
Strong understanding of configuration architecture including bitstream, protocols, boot flows, security, readback and debug
Deep appreciation of trade-offs across reliability, performance, power, and robustness
Proven advocate and practitioner of Partial Reconfiguration at system scale
Experience in ASIC/SoC design, enabling effective integration with hardened subsystems and modern interconnects
Ability to bring clarity to complex problems and influence technical direction across organizations
BS, MS, or PhD in Electrical/Computer Engineering or related field
Recognized technical leader in FPGA systems or architecture with significant architectural contributions, patents, publications, or industry impact

Nice To Haves

Strong Expertise in FPGA configuration, Partial Reconfiguration, and bitstream architecture
Experience with readback/debug infrastructure and field diagnostics
Background in ASIC/SoC design flows
Familiarity with FPGA toolchains (synthesis, P&R, PR flows)
Ability to define architecture across silicon, tools, and software layers

Responsibilities

Own FPGA configuration architecture, including bitstream, boot flows, interfaces, compression, security, and reliability
Define next‑generation Partial Reconfiguration architecture for low‑latency, secure dynamic updates
Drive innovation in runtime reconfiguration for high‑availability and adaptive systems
Architect readback, debug, and observability infrastructure for validation and in‑field diagnostics
Define configuration security, including secure boot, key management, and update flows
Drive system trade-offs across configuration bandwidth, latency, and power, including memory and interconnect interactions
Develop clear architecture specifications for configuration, PR, and debug subsystems
Align with software/tools teams for end‑to‑end configuration and PR flows
Collaborate with silicon and design teams for scalable high‑quality implementation
Influence product roadmap and customer engagement for PR‑driven solutions
Mentor architects and elevate FPGA architecture standards across the organization