FE Engineer

Apple•Cupertino, CA

2d•$174,149 - $225,300•Onsite

About The Position

Work on front-end design synthesis and large chip integration. Work timing analysis, formal verification, and lint checks. Design multi-clock and multi-power-domain. Understand floor-planning, placement, congestion, and setup/hold timing closure and working hands on with ECOs for functionality and timing. Propose logically equivalent RTL transforms to reduce power and area. Script, program, and work with DFT insertion. Work on RTL - System Verilog or VHDL. Work on CPUs, GPUs, or DSPs. RTL to netlist generation, working collaboratively with the RTL and Physical design teams. Deliver key netlist quality milestones for partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. PPA optimization of the netlist, working collaboratively with the RTL and Physical design teams. Deliver key netlist quality milestones for partition and be involved in understanding and improving current methodologies.

Requirements

Bachelor’s degree or foreign equivalent in Robotics Engineering, Electrical Engineering, Electronics Engineering, or a related field.
Using hardware description coding language (RTL) such as System Verilog, Verilog or VHDL.
Logic Synthesis using a synthesis tool such as Synopsys Design Compiler or Cadence Genus
Utilizing Unix or Linux and scripting capabilities in TCL, Perl or Python.
Statistical timing analysis in industry tools.
Analyzing timing and area reports and implementing improvements.
Using industry standard tools to perform Lint structural checking, clock CDC or reset domain crossing RDC analysis.
Using logic equivalence flow tools to check synthesis results for correct logic equivalent translation of RTL to gate.
Datapath design using knowledge of SOC, CPU or GPU subcomponent related designs.

Responsibilities

Work on front-end design synthesis and large chip integration.
Work timing analysis, formal verification, and lint checks.
Design multi-clock and multi-power-domain.
Understand floor-planning, placement, congestion, and setup/hold timing closure and working hands on with ECOs for functionality and timing.
Propose logically equivalent RTL transforms to reduce power and area.
Script, program, and work with DFT insertion.
Work on RTL - System Verilog or VHDL.
Work on CPUs, GPUs, or DSPs.
RTL to netlist generation, working collaboratively with the RTL and Physical design teams.
Deliver key netlist quality milestones for partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities.
PPA optimization of the netlist, working collaboratively with the RTL and Physical design teams.
Deliver key netlist quality milestones for partition and be involved in understanding and improving current methodologies.