FE Engineer

Apple • Austin, TX

1d • Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Austin, Texas. Execute development, assessment and refinement of RTL design to target power, performance, area and timing goals. Support testbench development and simulation for functional and performance verification. Explore high performance strategies and validate that RTL design meets targeted performance. Work with multi-functional engineering team to implement and validate physical design.

Requirements

• Utilizing verilog to write RTL for core IPs
• Performing RTL design with complex FSMs, and power savings features
• Using cache coherency protocols and interfaces
• Using advanced hardware prefetching techniques and algorithms
• Utilizing debugging tools (e.g. Verdi), and architecture models for day-to-day maintenance of RTL code
• Performing high-level micro-architecture, including designing new features for improving performance, power and timing of the chip
• Analyzing timing paths using industry standard tools, and understanding of gate-level design.
• Using LEC/LEQ tools and doing ECOs
• Low power design concepts and implementation, including clock gating, power gating, bus gating, and reducing gate paths.

Responsibilities

• Execute development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Support testbench development and simulation for functional and performance verification.
• Explore high performance strategies and validate that RTL design meets targeted performance.
• Work with multi-functional engineering team to implement and validate physical design.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior