Executive Director of R&D Engineering for 3DIC-Advance Packaging

Synopsys•Irvine, CA

155d•$233,000 - $349,000•Onsite

About The Position

SYNOPSYS IS THE LEADER IN ENGINEERING SOLUTIONS FROM SILICON TO SYSTEMS, ENABLING CUSTOMERS TO RAPIDLY INNOVATE AI-POWERED PRODUCTS. WE DELIVER INDUSTRY-LEADING SILICON DESIGN, IP, SIMULATION AND ANALYSIS SOLUTIONS, AND DESIGN SERVICES. WE PARTNER CLOSELY WITH OUR CUSTOMERS ACROSS A WIDE RANGE OF INDUSTRIES TO MAXIMIZE THEIR R&D CAPABILITY AND PRODUCTIVITY, POWERING INNOVATION TODAY THAT IGNITES THE INGENUITY OF TOMORROW. You have spent the better part of two decades building semiconductor solutions that actually ship, not just pass design reviews, and you know that the hardest problems in 3DIC are never just technical. They live at the intersection of physics, economics, and customer reality. You understand that a chiplet architecture is only as good as the yield curve it produces and the system performance it enables, and you have made the tradeoffs enough times to know which ones matter. You lead organizations that span continents and disciplines, and you have learned that the difference between a team that delivers and one that stalls is usually clarity. Clarity of purpose, clarity of decision rights, clarity of what good looks like. You do not manage by deck, you manage by walking into a room, understanding the blocker, and removing it. You have credibility with customers because you have been in the room when a design did not work and you helped fix it. You have credibility with engineers because you still understand the signoff flow. You think in roadmaps, not features, and you know how to translate a market shift into a three-year technical plan that your team can actually execute. At Synopsys, you will shape the future of heterogeneous integration for AI and high-performance computing, and the team you build will define what is possible.

Requirements

Bachelor's or Master's degree in Electrical Engineering or a related technical discipline, or equivalent professional experience with demonstrated technical leadership in semiconductor design
15+ years of hands-on experience in the semiconductor industry with deep expertise in advanced packaging, 3DIC technologies, chiplet architectures, and heterogeneous integration
Proven track record building and leading large, geographically distributed engineering organizations that have delivered complex 3DIC or advanced packaging solutions from architecture through production
Deep technical command of 3DIC-specific design and signoff challenges including signal integrity, power integrity, thermal management, mechanical stress, reliability physics, and yield optimization
Demonstrated ability to define and execute multi-year technology roadmaps for silicon IP or advanced packaging, balancing technical vision with business strategy and market requirements
Strong customer-facing leadership experience, including direct engagement with semiconductor customers, foundries, and ecosystem partners to define requirements, validate solutions, and drive adoption
Experience working effectively in highly matrixed, global organizations, influencing across EDA development, product management, go-to-market, manufacturing, and customer success teams without direct reporting authority

Nice To Haves

You can walk into a technical review with your team, identify the core issue in a complex 3DIC signoff problem, and outline a path forward that balances technical correctness with schedule reality
You build teams that want to work for you again, not because you are easy to work for, but because you are clear, you remove obstacles, and you give people hard problems they can actually solve
You can sit across the table from a VP of Engineering at a top five semiconductor company, understand their chiplet integration challenges, and translate that into a technical requirement your team can execute against
You make tradeoff decisions with incomplete information, and you are comfortable explaining the reasoning behind those decisions to both your team and executive leadership
You recognize when a technical plan is drifting from a business objective and you course-correct before it becomes a crisis, not after
You invest in the growth of your engineers, you know who is ready for the next level, and you create opportunities for them to get there

Responsibilities

Lead the global engineering organization responsible for 3DIC silicon IP and advanced packaging design, covering layout, physical design, signal integrity, power integrity, thermal modeling, and mechanical stress analysis for AI infrastructure and HPC products
Own the technical roadmap and execution strategy for chiplet architectures, heterogeneous integration, and die-to-die interconnect solutions that align with Synopsys business objectives and customer requirements
Drive cross-functional collaboration with EDA tool development teams, product management, go-to-market, and customer success to ensure Synopsys 3DIC solutions are differentiated, adoptable, and production ready
Engage directly with leading semiconductor customers and ecosystem partners to shape technical requirements, validate architectures, and accelerate adoption of Synopsys 3DIC and advanced packaging IP
Build, scale, and mentor a high-performing, multi-site engineering team, establishing a culture of accountability, technical excellence, and continuous improvement
Track and synthesize industry trends in 3DIC, chiplets, and advanced packaging, translating emerging technologies and competitive dynamics into actionable product and technology decisions
Make sound engineering tradeoffs across performance, power, area, cost, yield, and manufacturability, ensuring solutions meet both technical and business success criteria