EUV Mask Technology R&D Engineer

Micron • Boise, ID

6d

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron’s Mask Technology Center (MTC), we develop the materials, films, and processes that enable next‑generation EUV lithography. Our team collaborates across materials science, lithography, OPC, and high‑volume manufacturing to solve critical challenges in advanced DRAM scaling. We are a hands‑on, innovative group driving technologies that shape the future of High‑NA EUV. In this role, you will join an R&D team focused on next‑generation EUV mask materials and processes, helping drive readiness for High‑NA EUV manufacturing. You will contribute to technology roadmap development, partner with world‑class engineering teams and suppliers, and translate complex lithography requirements into robust, manufacturable mask solutions.

Requirements

• MS or PhD in Materials Science, Physics, Chemistry, Chemical Engineering, or a related field
• 2+ years of experience in semiconductor manufacturing, process development, or equivalent academic research in semiconductor technologies

Nice To Haves

• Direct experience in semiconductor mask, lithography, or wafer fabrication environments (EUV, DUV, or advanced nodes)
• Experience with actinic mask inspection, defect printability analysis, or mask repair
• Strong background in BEOL or FEOL process control, mask process qualification, or high-volume semiconductor manufacturing
• Experience defining tool requirements, specifications, and roadmap strategy for semiconductor material, equipment, or processes
• Proven track record working with semiconductor equipment suppliers and engaging in early-stage tool or process development
• Hands-on experience with EUV or High-NA EUV mask/wafer technology development
• Deep understanding of lithography fundamentals, including EUV systems, mask-to-wafer correlation, and pattern transfer fidelity
• Experience with lithography simulation, OPC, or mask pattern design for advanced nodes.

Responsibilities

• Develop EUV mask blank materials and processes, including film stack design, deposition, etch, clean, and patterning quality
• Advance High‑NA EUV readiness through material selection, mask design, stitching, lithography performance optimization, and lifetime improvement
• Translate lithography requirements into manufacturable mask solutions in collaboration with OPC, design, and lithography teams
• Conduct data‑driven R&D using DOE and fundamental analysis to improve yield, reliability, and manufacturability
• Collaborate with cross‑functional engineering teams to transition new technologies into FEOL process engineering

Benefits

• choice of medical, dental and vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• robust paid time-off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level