Engineer/Sr. Eng/Prinicipal - NAND CMOS DTCO

Micron Technology • San Jose, CA

2d • $111,000 - $189,000

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Requirements

• PPAC targets
• process capability
• device limits
• design rules
• interconnect
• device/test monitors
• performance
• area
• RC
• reliability
• models
• silicon learning
• pathfinding
• containment

Responsibilities

• Define and converge PPAC targets with strong linkage to process capability and device limits.
• Translate targets into design rules (incl. interconnect) and device/test monitors.
• Drive trade‑offs across process/device capability and IC/interconnect design to optimize performance, area, RC, and reliability.
• Ensure alignment across targets → design rules → models → design usage.
• Own model enablement and QA, keeping models consistent with silicon learning.
• Support pathfinding and containment to close PPAC gaps early.

Benefits

• choice of medical, dental and vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• robust paid time‑off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Education Level: No Education Listed