Engineer II - Design

Microchip Technology Inc.•San Jose, CA

4d•$70,304 - $143,000

About The Position

Join Microchip Technology’s Design Engineering team as an Engineer II—Design, responsible for compute-in-memory neural network modeling and algorithm implementation. The role supports architecture development, RTL and circuit design, integration, verification, performance, power, area, documentation, and the product lifecycle. The Engineer independently executes defined assignments, partners with relevant technical and business stakeholders, and helps deliver reliable, high-quality engineering outcomes while driving continuous improvement.

Requirements

Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field.
2.5–5 years of experience or research in neural network modeling for compute-in-memory or neuromorphic computing.
Knowledge of neural network architectures, such as multilayer perceptrons (MLPs), gated recurrent units (GRUs), CNNs, and small language models (sLLMs).
Experience with neural network modeling for compute-in-memory systems.
Strong written and verbal communication skills.
Reliability, accountability, and a record of sustained contributions in prior roles.
Effective teamwork and cross-functional collaboration.
Integrity and accuracy when representing qualifications, experience, and credentials.

Nice To Haves

PhD in Electrical Engineering, Computer Science, or a related field.
Experience with RISC-V architecture.
Knowledge of nonvolatile memory technologies.
Knowledge of VLSI design flows.
Knowledge of computer architecture.
Experience with validation, debugging, and testing.
Experience with CAD and design tools, such as HSPICE/HSIM, Verilog, and Cadence Design Entry.
Knowledge of programming and scripting languages, such as Python, Tcl, C++, or SystemC.
Knowledge of semiconductor device physics.

Responsibilities

Develop neural network models for architectures such as convolutional neural networks (CNNs), transformers, large language models (LLMs), and recurrent neural networks (RNNs) for analog compute-in-memory (ACIM) systems.
Model variation and mismatch across ACIM components.
Model the power, performance, and area (PPA) of ACIM solutions.
Implement ACIM algorithms.
Contribute to ACIM hardware architecture development.
Coordinate with engineers across design, technology, process, and test teams to advance ACIM technology.
Translate product specifications, neural network performance targets, and schedule needs into design requirements and plans.
Analyze specifications, simulations, timing, power, area, integration, risks, dependencies, and technical trade-offs for ACIM solutions.