Engineer, GPU RTL Design - Pixel Pipe

Samsung•San Jose, CA

2d•Onsite

About The Position

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. As a GPU RTL Design Engineer, you will work on designing and developing complex RTL blocks and subsystems for Samsung’s next-generation mobile GPU IPs, delivering high-quality, scalable implementations that power premium smartphones and adjacent consumer technologies. You bring curiosity, foundational RTL design knowledge, and microarchitectural understanding to support design decisions, resolve cross-block challenges, and help ensure robust designs across multiple GPU functional domains—including control, datapath, memory systems, and fixed-function logic, with a focus on pixel processing and graphics pipeline stages. You work on the microarchitecture definition and RTL implementation of complex GPU blocks and subsystems, translating architectural specifications into efficient, maintainable, and scalable hardware designs, including pixel pipeline and fixed-function graphics logic. You support the RTL design lifecycle from microarchitecture through RTL development, integration, debug, and simulation readiness while collaborating across multiple functional areas and projects. You help drive design quality and accuracy by developing clean, synthesizable RTL and collaborating with verification teams to resolve functional issues and improve coverage and robustness across graphics processing flows. You collaborate with RTL design engineers and cross-functional teams to help address interface definition, timing, power, performance, and area (PPA) considerations throughout the design cycle. You take ownership on assigned tasks and help advance best practices, methodologies by exploring emerging GPU technologies and RTL design methodologies.

Requirements

Bachelor’s Degree in Computer Science, Computer Engineering, or relevant field.
Knowledge of semiconductor RTL design for complex SoC, CPU, or GPU architectures.
Experience with RTL design using Verilog/SystemVerilog, including microarchitecture development, integration, and debug.
Exposure to GPU or high-performance digital design concepts, including control logic, datapath design, memory systems, and fixed-function acceleration.
Exposure to front-end ASIC design flows, including linting, synthesis, timing analysis, and simulation tools.
Strong analytical, and problem-solving skills, with the ability to identify and propose data-driven solutions.
Good communication and collaboration skills, with the ability to navigate ambiguity a fast-paced, global team environment.

Nice To Haves

Familiarity with GPU, graphics, or pixel processing concepts is preferred.

Responsibilities

Work on the microarchitecture definition and RTL implementation of complex GPU blocks and subsystems, translating architectural specifications into efficient, maintainable, and scalable hardware designs, including pixel pipeline and fixed-function graphics logic.
Support the RTL design lifecycle from microarchitecture through RTL development, integration, debug, and simulation readiness while collaborating across multiple functional areas and projects.
Drive design quality and accuracy by developing clean, synthesizable RTL and collaborating with verification teams to resolve functional issues and improve coverage and robustness across graphics processing flows.
Collaborate with RTL design engineers and cross-functional teams to help address interface definition, timing, power, performance, and area (PPA) considerations throughout the design cycle.
Take ownership on assigned tasks and help advance best practices, methodologies by exploring emerging GPU technologies and RTL design methodologies.