Engineer, ASIC Design Verification

Ayar Labs • San Jose, CA

12h • $130,000 - $150,000 • Onsite

About The Position

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking an Entry-Level Digital Verification Engineer to join our hardware engineering team. In this role, you will help verify digital designs used in semiconductor, FPGA, ASIC, or SoC products. You will work closely with design engineers, verification engineers, and system architects to ensure that digital circuits meet functional, performance, and quality requirements before production. This is an excellent opportunity for a recent graduate or early-career engineer interested in digital logic, computer architecture, hardware verification, and semiconductor development.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Basic understanding of digital logic design concepts, including finite state machines, pipelines, registers, memory, and timing.
• Familiarity with Verilog, SystemVerilog, or VHDL.
• Exposure to simulation and debugging tools.
• Basic programming or scripting experience in Python, Perl, Tcl, C/C++, or similar languages.
• Strong analytical and problem-solving skills.
• Ability to work in a collaborative engineering environment.
• Good written and verbal communication skills.

Nice To Haves

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Academic or internship experience with ASIC, FPGA, or SoC verification.
• Familiarity with UVM or object-oriented programming concepts.
• Experience using EDA tools from Synopsys, Cadence, Siemens EDA, or similar vendors.
• Understanding of computer architecture, bus protocols, or embedded systems.
• Knowledge of coverage-driven verification.
• Experience with version control tools such as Git.
• Familiarity with Linux-based development environments.

Responsibilities

• Develop and execute verification test plans for digital blocks, subsystems, or SoC-level designs.
• Create and maintain testbenches using SystemVerilog, UVM, Verilog, or related verification methodologies.
• Write directed and constrained-random tests to validate design functionality.
• Debug simulation failures and work with design engineers to identify root causes.
• Develop functional coverage models and track verification progress.
• Run regressions and analyze simulation results.
• Support verification of RTL designs for ASIC, FPGA, or SoC projects.
• Document verification results, issues, and test procedures.
• Participate in design and verification reviews.
• Learn and apply industry-standard verification tools and methodologies.

Benefits

• Hands-on experience with digital verification methodologies.
• Exposure to ASIC, FPGA, or SoC development flows.
• Mentorship from experienced design and verification engineers.
• Opportunity to work on real-world hardware products.
• Career growth path toward verification engineering, design engineering, SoC architecture, or validation engineering roles.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level