Emulation Engineer

MatX • Mountain View, CA

1d • Hybrid

About The Position

MatX is building a compute platform for AGI, developing vertically integrated full-stack solutions from silicon to systems, including hardware and software, to train and run the largest ML workloads for AGI. MatX is seeking Emulation engineers to join their team to create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies. Specifically, they are hiring a Senior/Staff Emulation Engineer to build the infrastructure, flows, and debug methodology behind their advanced connectivity SoCs. This role sits within the Emulation team but has a broader impact, creating reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation. The ideal candidate is a multi-disciplinary engineer with an out-of-the-box, can-do mindset, comfortable moving between RTL, software, tooling, system debug, and vendor flows. A reuse-first mindset, strong software instincts, and the ability to learn quickly across boundaries are essential.

Requirements

• Strong hands-on experience with SoC emulation or system-level validation.
• Experience with at least one commercial emulation platform, such as Palladium.
• Working Verilog/SystemVerilog and waveform-debug skills — enough to develop a custom transactor or agent when needed (with or without AI assistance).
• Strong software and automation skills — Python plus one or more of C, C++, Rust, Tcl, or shell.
• Demonstrated ability to build tools and infrastructure, not just run existing flows.
• Strong system-level debug instincts spanning RTL, firmware, and software.
• Ability to work independently and across functional and team boundaries.
• Must be authorized to work in the United States.
• Must work from offices in Mountain View Tuesdays-Thursdays.
• Must be capable of performing job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

Nice To Haves

• UVM or hybrid SoC testbench development.
• Integrating cycle-accurate, software, or reference models into emulation/DV flows.
• Rust in verification or emulation flows (or strong interest in adopting it).
• Bazel or large-scale build/regression systems.
• Reusable stimulus across simulation, emulation, and post-silicon.
• AI/LLMs used to build real engineering tools — debug, triage, flow generation — beyond chat prompting.
• Connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics.
• Firmware or driver bring-up on emulation platforms.
• Scaling emulation or verification infrastructure across multiple projects or product lines.

Responsibilities

• Define and execute emulation strategy and test plans for complex connectivity SoCs.
• Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu or Veloce.
• Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and memory models — for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and (Q)SPI. Build custom transactors where needed.
• Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests.
• Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows — including developing new transactors and agents from scratch when off-the-shelf options don't fit.
• Drive emulation speed-ups and resource utilization — compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and waveform/trace management.
• Build automation for regression triage, debug, model usability, and engineering productivity.
• Go beyond prompting with AI — build practical LLM-based tooling for log analysis, waveform triage, debug assistance, and flow generation, including custom skills, agents, rules, and workflows that fit the engineering stack.
• Collaborate with architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams.

Benefits

• 4 weeks PTO (accrued)
• 12 company Holidays
• Up to 3 weeks remote work
• Company-subsidized Medical (Kaiser or Anthem) for employees & dependents
• Guardian Dental and Vision insurances for employee & dependents
• Life insurance (employee only)
• HSA and FSA offerings via Lively
• Roth IRA/ 401K (or both) retirement plans with up to 5% company contribution to 401K
• 100% company-paid life insurance (up to $300K)
• $1500 Professional Development Budget (per year)
• Onsite team lunch & dinner Monday - Friday
• Commute on company Uber account, or reimbursement for train rides
• $50/mo to use on perk of choice
• $35/mo for cellular reimbursement
• $40/mo for wifi reimbursement
• 100% paid mental health benefit via SpringHealth and Guardian EAP
• Up to 12 weeks paid parental leave
• 10 weeks pregnancy disability leave
• Flexible return-to-work hours
• Benepass reproductive health & parental benefit
• Up to $20K/month in AI Resources
• Dedicated internal AI Tooling Team

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed