Emulation Engineer, Lead

Positron Corporation

2d•$180,000 - $300,000

About The Position

As a Lead Emulation Engineer, you will provide technical leadership for the pre-silicon validation of Positron.ai’s next-generation AI inference ASIC. You will own the end-to-end emulation strategy on the Cadence Palladium platform—architecting complex model builds, managing multi-rack partitioning, and driving the 'left-shift' of our software development. You will collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you will set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.

Requirements

Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3), including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
Expert-level Python, Tcl, and Bash skills to build and maintain the infrastructure for automated model releases and nightly regressions
Proficiency in debugging low-level firmware and kernel-level issues using Verdi, SimVision, and hardware-software co-debug tools
BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
8+ years in ASIC Emulation or Verification, with significant experience on large-scale Palladium installations
Mastery of SystemVerilog, Verilog, and C/C++ for transactor development and reference modeling.
Deep understanding of data center protocols including PCIe, DDR and AMBA AXI/NoC

Responsibilities

Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
Create and maintain the hybrid emulation and co-simulation environments (using SCE-MI or DPI) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
Design and execute comprehensive emulation test plans to verify high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and complex AI memory hierarchies.
Utilize Palladium’s Dynamic Power Analysis (DPA) and throughput monitors to identify "true peaks" and performance bottlenecks that simulation cannot capture.
Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest Palladium Z3 capabilities.