Embedded Systems Engineer

Digantara•Denver, CO

3d•Onsite

About The Position

Digantara U.S. is seeking an experienced and driven Embedded Systems Engineer to determine whether the company's analytical workflows can be deployed on spaceflight and other resource-constrained processing platforms, and provides the deployment reality constraint for algorithm and model development. The role profiles workflows across representative processing architectures, identifies where processing time, memory, and power are consumed, and determines what can be partitioned, accelerated, simplified, or removed. Findings are captured in defensible trade studies and technology-maturation roadmaps suitable for customer and follow-on program review. Emphasis is placed on the characteristics that determine operational value: false-positive behavior under degraded observations, calibration of confidence metrics suitable for operator use, and inference cost compatible with constrained onboard processing. The role works closely with astrodynamics and embedded-systems staff to ensure models reflect genuine dynamical structure and remain deployable within onboard resource limits.

Requirements

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus [5] + years of embedded-systems experience, including work on space, avionics, or other constrained, high-reliability platforms.
Strong C/C++ and Python, with the ability to prototype using AI coding agents and profile and optimize numerically intensive code.
Demonstrated experience with at least one radiation-hardened or radiation-tolerant processing platform, and working familiarity with the broader landscape.
Hands-on FPGA experience: VHDL or Verilog, HLS toolchains, and sound judgment about appropriate hardware/software partitioning.
Real-time and resource-constrained system design: SWaP budgeting, latency analysis, and deterministic memory management.
Ability to produce trade studies that withstand technical review, with stated assumptions, bounded uncertainty, and conclusions traceable to data.
Must be able to obtain and hold a U.S. security clearance.

Nice To Haves

Spaceflight heritage: hardware that has flown, or that progressed far enough through qualification to demonstrate its demands firsthand.
Experience deploying ML inference to embedded or FPGA targets (quantization, fixed-point conversion, accelerator IP).
Familiarity with spacecraft avionics architecture, onboard data handling, and flight-software standards (DO-178C, NASA NPR 7150.2, or similar).
Working knowledge of onboard cryptographic implementation and key-management.
Prior SBIR/STTR or comparable government R&D experience, including authoring roadmap and transition-planning material.

Responsibilities

Profile analytical workflows across candidate onboard processing architectures, including radiation-hardened and radiation-tolerant classes such as BAE RAD5545, Cobham GR740, Microchip PolarFire SoC RT/MV variants, Xilinx KU060-class rad-tolerant FPGAs, Mercury TR-MX1, Aitech S-A1760, and rad-screened NVIDIA platforms.
Characterize throughput, memory footprint, latency, and power for each candidate, using measured data where hardware or representative surrogates are available and clearly bounded estimates otherwise, with the basis for each clearly identified.
Identify and quantify computational bottlenecks by pipeline stage and platform class.
Develop CPU/FPGA partitioning options and identify candidate functions for hardware acceleration, with assessment of the associated engineering cost.
Work with data-science and astrodynamics staff on algorithmic simplification opportunities (reduced-order propagation, fixed-point arithmetic, model compression) quantifying the performance cost of each rather than assuming it negligible.
Assess radiation-environment implications for the relevant orbital regimes: SEU/SEFI rates, mitigation approaches (TMR, scrubbing, checkpointing).
Contribute the onboard-processing portion of reference architectures: processing-element definition, data flow, interfaces to sensing and communications, and encrypted alert-generation paths.
Develop technology-maturation roadmaps: critical technology element identification, TRL progression logic, hardware-in-the-loop validation approaches, and transition pathways such as hosted-payload and rideshare deployment. Produce calibrated confidence metrics suitable for downstream operational use, documented precisely enough to support operator decisions.