Electro-Optic Link Hardware Engineer

Lightmatter • Boston, MA

16d • Hybrid

About The Position

Lightmatter is seeking a hands-on photonics engineer to lead verification and characterization of high-speed electro-optic links across multiple silicon and system programs. The engineer will work at the bench alongside the EOE team, own modeling methodology and measurement standards, and serve as an escalation point for challenging signal-integrity and link-performance problems. The role combines hands-on laboratory work with ownership of verification strategy, modeling, and technical guidance for engineers.

Requirements

• MS or PhD in EE, Photonics, or Physics with 8 or more years of experience, or BS/MS with 10 or more years of experience.
• Ownership of verification strategy for a full silicon or system program.
• Deep expertise in 56G/112G/224G+ serial links, SerDes equalization (CTLE/FFE/DFE), and signal integrity, including S-parameters, crosstalk, and link budgets.
• Hands-on laboratory experience leading investigations that had stalled others.
• Strong Python or MATLAB skills for automation frameworks used by a team.
• Proficiency with VNAs, oscilloscopes, BERTs, TDRs, and tools such as ADS, HFSS, Cadence, and COMSOL.
• Track record of mentoring engineers.
• Capacity to comply with federally mandated U.S. export control requirements.

Nice To Haves

• Silicon photonics or electro-optic systems experience at the architecture level.
• Package, PCB, or channel co-design ownership.
• COM/IBIS-AMI modeling experience.
• Patent or standards contributions, such as to OIF or IEEE 802.3.

Responsibilities

• Run hands-on laboratory characterization and debug of high-speed electrical and optical hardware, including novel failure modes.
• Build system-level electrical, optical, and electro-optic channel models and correlate them with bench measurements.
• Own link-budget and verification methodology while performing validating measurements.
• Characterize eye diagrams, bit error rate (BER), jitter, equalization, and channel impairments.
• Support silicon bring-up and root-cause debugging with analog, package, PCB, and SerDes teams.
• Influence chip, package, and system architecture tradeoffs based on bench findings.
• Mentor Senior and Staff engineers while remaining hands-on with laboratory work.
• Build automation and tools to accelerate characterization.

Benefits

• Comprehensive health care plan covering medical, dental, and vision.
• Retirement savings matching program.
• Basic and voluntary life insurance, including AD&D.
• Generous time off, including vacation, sick time, and public holidays.
• Paid family leave.
• Short-term and long-term disability.
• Training and development.
• Commuter benefits.
• Flexible, hybrid workplace model.
• Equity grants for applicable full-time employees.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior