Summer 2027 - Electrical Engineering Internship, FPGA

CesiumAstro•Melbourne, FL

16h•Onsite

About The Position

CesiumAstro is hiring Summer 2027 FPGA interns to apply digital design and verification principles to FPGAs for satellite communication systems. Interns will work closely with CesiumAstro engineers across multiple phases of FPGA development and will primarily focus on either FPGA design or FPGA verification, based on project needs, experience, and interests. Assignments will be determined by project availability and candidates’ interests. FPGA design work may include developing and testing RTL for high-speed serial interfaces and data streams, digital processing cores, multiple clock domains, and management interfaces. FPGA verification work may include developing testbenches and verification environments, creating test scenarios, generating constrained-random stimulus, checking expected behavior, debugging failures, and measuring verification coverage. Prior FPGA-specific coursework or experience is not required. The company seeks candidates with a strong foundation in digital design or software-based verification concepts and an interest in applying those skills to FPGA development. Interns regularly present their work to peers, mentors, and executive leadership throughout the summer, so excellent written and verbal communication skills are required. The internship is compensated and onsite at one of CesiumAstro’s facilities. Applicants must meet U.S. space technology export-control eligibility requirements: be a U.S. citizen, lawful permanent resident, conditional resident, asylee, or refugee, or be eligible to obtain the required U.S. Department of State authorizations. Applicants are asked to include a cover letter describing their interest in digital design, FPGA development or verification, and space systems or communication systems, as well as their U.S. citizenship or permanent-resident status.

Requirements

Currently enrolled in a BS, MS, or PhD program in Electrical Engineering or Computer Engineering at an accredited university.
Understand fundamental digital design concepts, including combinational and sequential logic, finite state machines, timing, and synchronous digital systems.
Have digital design or hardware-description experience from coursework, research, personal projects, competition teams, internships, or other technical activities.
Demonstrate the ability to approach technical problems methodically, learn new concepts, and debug complex systems.
Have excellent written and verbal communication skills.
Meet the stated U.S. space technology export-control eligibility requirements.
Include a cover letter describing relevant interests and U.S. citizenship or permanent-resident status.

Nice To Haves

FPGA development or verification experience through coursework, research, internships, personal projects, or extracurricular activities.
Experience with SystemVerilog, Verilog, VHDL, or UVM.
Experience with FPGA or HDL development tools such as AMD/Xilinx Vivado, Questa/ModelSim, or similar tools.
Experience in digital signal processing.
Experience with embedded systems or board-level digital hardware.
Coursework or experience in communication systems.

Responsibilities

Work with CesiumAstro engineers on FPGA development through multiple phases of the development process.
Depending on assignment, develop and test RTL for high-speed serial interfaces and data streams, digital processing cores, multiple clock domains, and management interfaces.
Depending on assignment, develop testbenches and verification environments; create test scenarios; generate constrained-random stimulus; check expected behavior; debug failures; and measure verification coverage.
Present work to peers, mentors, and CesiumAstro executive leadership throughout the summer.