EDA Tools SW Engineer

Intel Corporation•Austin, TX

2d•$173,660 - $330,340•Hybrid

About The Position

The Technical Lead position within the Design Enablement (DTP) organization of Intel Foundry is a Design Enablement Applications and Support Technical Lead position chartered to lead a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test chips when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions. Lead and develop a high-performing engineering team by setting priorities, driving execution across organizational boundaries, and fostering an inclusive and collaborative work environment. Provide technical leadership, mentoring, and coaching while ensuring delivery of engineering objectives aligned with schedule, quality, and cost targets. Direct and coordinate engineering activities, allocate resources effectively, and drive problem resolution through sound technical judgment. Promote team values, accountability, and continuous improvement while guiding employee development, performance, and productivity. Exercise independent judgment in addressing complex challenges that may require deviation from standard practices.

Requirements

BS degree with 10+ years of experience or MS degree with 8+ years of experience or PhD degree with 6+ years of experience in Electrical Engineer or Computer Engineering or related field.
6+ years of experience in two or more of the following: Technical management or lead experience mentoring or leading medium sized teams.
Experience with Test chip physical verification and tape-in
Intel and/or external foundry process technology knowledge in advance nodes.
Industry direct experience and in-depth knowledge to support customers in ASIC/Physical Design and/or Physical Verification/runsets, in advanced technology nodes, or EDA tools.
Experience with technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.

Nice To Haves

Experience in advanced-node semiconductor design and verification methodologies.
Experience with customers and stakeholders to resolve complex design and technology challenges.

Responsibilities

Lead and develop a high-performing engineering team by setting priorities, driving execution across organizational boundaries, and fostering an inclusive and collaborative work environment.
Provide technical leadership, mentoring, and coaching while ensuring delivery of engineering objectives aligned with schedule, quality, and cost targets.
Direct and coordinate engineering activities, allocate resources effectively, and drive problem resolution through sound technical judgment.
Promote team values, accountability, and continuous improvement while guiding employee development, performance, and productivity.
Exercise independent judgment in addressing complex challenges that may require deviation from standard practices.
Drive customer solutions for ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test chips when customers use Intel PDK collaterals in these domains.
Partner and leverage domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions.