DV Intern - Spring 2027
Etched•San Jose, CA
•Onsite
About The Position
As a Design Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Requirements
- Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Able to learn quickly about transformers and other aspects of modern artificial intelligence
Nice To Haves
- Familiarity with transformer models and machine learning
- UVM or formal verification experience
- Ability to program with Python or another scripting language
Responsibilities
- Ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready.
- Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Benefits
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
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What This Job Offers
Career Level
Intern
Education Level
No Education Listed
