DRAM Firmware (FW)/Integration Engineer

Omm IT Solutions•Rancho Cordova, CA

4d•Onsite

About The Position

This is a 100% onsite contract role in Rancho Cordova, CA, requiring the engineer to work from the office five days a week. The position involves developing, validating, and integrating DRAM drivers for the SSD FW platform. The engineer will gain expertise in DRAM IP on the controller side, including read, write, gate trainings, and write leveling. They will also develop expertise in DRAM PHY IP configuration, DRAM ECC, and DDR4 and DDR5 protocols, including mode register configuration and validation, as well as DDR4/DDR5 initialization development and validation. The role requires building and maintaining relationships with internal and external teams, providing technical expertise to cross-functional teams, and documenting requirements and tracking schedules.

Requirements

Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
Minimum 3 years of experience in the following areas, obtained through schoolwork, classes, research, previous job experience, and/or internship experience.
Good understanding of DRAM architecture, operation, and integration.
Proficiency with memory testing tools and software.
Knowledge of signal integrity, high-speed signal fundamentals, and simulation techniques.
Hands-on experience with lab tools such as oscilloscopes, power supplies, and soldering equipment.
Good analytical skills and ability to understand and communicate complex concepts.
Strong planning and documentation skills.
Good communication, interpersonal, and problem-solving skills.
Ability to work independently and in a team environment.
Develop test procedures and tools for DRAM validation and debugging.

Nice To Haves

Strong HW or FW project management and leadership skills.
Develop and validate DDR power states and refresh policy.
Guide debug efforts to resolve DRAM issues.

Responsibilities

Develop, validate, and integrate DRAM drivers for the SSD FW platform.
Understand DRAM IP on the controller side and develop and validate read, write, gate trainings, and write leveling.
Develop expertise in DRAM PHY IP and configure it.
Develop expertise in DRAM ECC.
Develop expertise in DDR4 and DDR5 protocols.
Configure DDR4/DDR5 mode registers and validate those register settings.
Develop and validate DDR4/DDR5 initialization.
Build and maintain close relationships with internal and external teams.
Provide technical expertise to cross-functional teams.
Document requirements and track schedules related to each product.