DRAM Device & Cell Technology Engineer

Micron Technology • Boise, ID

1d • Onsite

About The Position

As a DRAM Device & Cell Technology Engineer at Micron’s Boise R&D site, you will play a central role in defining, developing, and optimizing next generation DRAM architectures, cell technologies, and access device technologies. You will collaborate closely with device engineers, process integration teams, process teams, modeling groups, design teams, and product engineering partners to push the limits of density, performance, reliability, and manufacturability for future DRAM nodes. This position is highly technical and hands on, requiring deep knowledge of device physics and semiconductor processing. Strong experimental design skills, and the ability to translate data into device, design, integration, or process innovations is required.

Requirements

• M.S. or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, or related field.
• Strong understanding of semiconductor device physics (MOSFETs, access devices, capacitors).
• Experience with electrical characterization, device testing, and data analysis.
• Familiarity with DRAM operation fundamentals (activation, sensing, disturb mechanisms).
• Proficiency with scripting and data analysis tools (Python, MATLAB, JMP, etc.).

Nice To Haves

• Ability to communicate experimental results clearly and drive cross‑team alignment.
• Hands‑on experience with DRAM or NAND device development.
• TCAD simulation experience (Synopsys Sentaurus, Silvaco).
• Experience with semiconductor device fabrication or advanced BEOL integration.
• Knowledge of reliability mechanisms and device variation analysis.

Responsibilities

• Define electrical targets for access devices, capacitors, and cell stack elements.
• Evaluate new cell structures, materials, and integration schemes to improve density, retention, disturb immunity, and sensing margins.
• Partner with modeling teams to validate device/cell behavior against TCAD and compact models.
• Design and implement experiments on silicon: Perform in‑depth electrical characterization: ION/IOFF distributions, Vt extraction, retention behavior, disturb mechanisms, leakage paths, and variation analysis.
• Extract insights from large data sets using statistical methods; propose actionable design or process improvements.
• Analyze array‑level behaviors such as activation, sensing, disturb interactions, and read window margin.
• Work with circuit teams on WL/BL drivers, sense amplifier interactions, and operation sequence optimization.
• Work with internal groups and manufacturing sites to ensure robustness and scalability of developed solutions.
• Support technology transfer from R&D to high‑volume manufacturing.
• Participate in defining DRAM scaling paths (3D DRAM, new device concepts, capacitor innovations, new materials).
• Benchmark internal versus industry device/cell capabilities and propose strategy adjustments.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time‑off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior