DMTS, DRAM Systems

Micron•San Jose, CA

About The Position

Micron Technology is seeking a Distinguished Member of Technical Staff to lead architecture analysis for AI, cloud, and enterprise platforms, from memory devices through racks and data centers. The role connects DRAM architecture, device organization, electrical, thermal, and power behavior with system modeling and analysis, translating findings into product and roadmap decisions for future DRAM, LPDDR, HBM, CXL, SSD, and disaggregated memory solutions. The successful candidate will analyze DRAM and LPDRAM components and circuit designs across competitive products and develop forward-looking direction for architecture and design teams. The position involves evaluating memory technologies and their system-level effects, comparing generations and competing solutions, and quantifying performance, power, cost, reliability, thermal, and architectural tradeoffs. The role drives full-stack architecture co-optimization and provides actionable recommendations to architecture teams. It also serves as a technical leadership position, influencing decisions across business units, guiding modeling and simulation strategy, mentoring senior architects and engineers, and representing Micron in industry and standards forums. The role incorporates Micron-approved AI tools into analysis and modeling workflows, with human review and responsible governance of AI-generated results. This is a full-time position. The stated US base salary range is $216,000 to $430,000 per year. Additional compensation may include benefits, bonuses, and equity.

Requirements

PhD or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
15 or more years of experience in memory or storage architecture, system architecture, or performance engineering.
Deep expertise in memory or storage systems, from device and electrical behavior through system-level performance.
Demonstrated ability to influence product direction through quantitative analysis.
Strong record of patents, publications, or industry technical leadership.
Ability to turn complex analysis into clear recommendations for architecture and business stakeholders.
Ability to own decisions involving AI and apply responsible AI practices and AI governance policies.

Nice To Haves

Experience across volatile and non-volatile memory, such as DRAM, HBM, NAND, or SSD, and understanding of their interaction in the memory and storage hierarchy.
Knowledge of DRAM device topology, channel/rank/bank behavior, timing, training, signaling, and package-level effects.
Hands-on experience applying AI/ML or GenAI to performance modeling, workload characterization, data analytics, or engineering productivity.
Experience with memory or SSD controller architecture, firmware, ECC and RAS, or thermal and power management.
Experience working with product planning or business units to influence roadmaps.

Responsibilities

Build a deep understanding of DRAM architecture, device organization, and layout effects across DDR4, DDR5, LPDDR5/5X/5T, HBM, and emerging memory.
Analyze memory technologies’ electrical margins, signaling, thermal behavior, power, and performance, and determine their effects at the system level.
Compare memory generations, configurations, and competing solutions to identify performance, power, cost, and architectural gaps.
Quantify tradeoffs involving cost per GB, power efficiency, latency, bandwidth, reliability, thermals, and controller and platform complexity.
Drive optimization across applications and frameworks, operating systems and runtime software, memory controllers and firmware, memory and storage subsystems, and network fabrics.
Provide architecture teams with actionable recommendations on memory features, controller requirements, training flows, power management, and reliability and RAS capabilities.
Advise on internal development needed to close gaps and improve competitiveness.
Influence architecture decisions across multiple business units as a recognized technical authority.
Partner with architecture, firmware, validation, product engineering, and business teams to define data requirements and agree on findings.
Produce competitive assessments and executive-level recommendations.
Define long-term modeling and simulation strategy and mentor senior architects and engineers.
Represent Micron in standards bodies such as JEDEC and the CXL Consortium, ecosystem initiatives, academic collaborations, and industry conferences.
Use Micron-approved AI tools for workload analysis, modeling, competitive assessment, and technical documentation.
Redesign modeling and analysis workflows to automate repetitive work with clear human review points and escalation paths.
Check AI-generated model outputs, data summaries, and competitive insights for accuracy, bias, and relevance before they inform decisions.
Build data-backed assessments of internal and competing memory technologies from device to system.
Establish modeling and simulation capabilities used by business units for roadmap decisions.
Identify and rank important performance, power, cost, and architecture gaps, and measurably influence future product definitions.
Demonstrate measurable gains in analysis speed or quality by incorporating AI into architecture and modeling workflows and helping the team adopt these practices.