Distinguished Technologist - AI Model Performance Architect

HP•Houston, TX

23h•Remote

About The Position

This role is responsible for bridging system memory architecture with AI model behavior, ensuring optimal performance through HW/SW co-design and workload-aware tuning. This role develops AI workload optimization strategies for faster model startup, improved inferencing efficiency, and reduced memory needs. This role leverages technical and business expertise to outline strategy roadmaps for the function. The role identifies future growth opportunities and addresses gaps with innovative solutions. The role collaborates closely with various stakeholders, empowers teams to achieve remarkable and consequential outcomes, and spearheads industry-leading research and development. This role also provides consultation, design input, and feedback for new product development and design reviews across multiple organizations and architectures. It works closely with product management and engineering stakeholders from related departments and empowers the teams to deliver outstanding and impactful results. It initiates industry-leading research and development, serving as a recognized lead authority internally and externally. It provides mentoring and guidance to less-experienced staff members to set an example of electrical hardware design and development, innovation, and excellence. It participates in and provides input on the process for selection of future technical leaders.

Requirements

Four-year or Graduate Degree in Electrical Engineering, or any other related discipline or commensurate work experience or demonstrated competence.
Typically has 12+ years of work experience, preferably in electrical design and tools, software packages, architecture of electronic hardware, or a related field.
Memory & AI model design
Computer Science
Debugging
Electrical Engineering
Electronic Engineering
Electronics
Field-Programmable Gate Array (FPGA)
Hardware Architecture
Hardware Design
MATLAB
Mechanical Engineering
New Product Development
Oscilloscope
Physics
Printed Circuit Board
Schematic Capture
Simulations
Systems Design
Effective Communication
Results Orientation
Learning Agility
Digital Fluency
Customer Centricity

Responsibilities

Analyze system bandwidth, latency, and compute bottlenecks
Model performance across CPU/GPU/NPU for AI workloads
Simulate workload execution (PnP tradeoffs, resource contention)
Optimize model execution (initialization time, caching, KV reuse)
Drive HW/SW co-design (memory, caching, scheduling)
Partner with ML teams to align model structure with system architecture
Leverages recognized technical and business expertise to define long-term vision and strategy for electrical hardware design and development across multiple feature areas and divisional boundaries.
Develops technology roadmaps for electrical/hardware engineering team; identifies gaps and solutions for future growth.
Communicates strategy and technology roadmaps to executive staff, industry partners and customers.
Provides innovative solutions and integrates advanced technologies, theories, or techniques with a significant impact across disciplines, championing large projects for long-range goals.
Provides consultation, design input, and feedback for new product development and design reviews across multiple organizations and architectures.
Works closely with product management, engineering stakeholders from related departments and empowers the teams to deliver outstanding and impactful results.
Initiates industry-leading research and development, serving as a recognized lead authority internally and externally.
Provides mentoring and guidance to less-experienced staff members to set an example of electrical hardware design and development, innovation, and excellence.
Participates in and provides input on process for selection of future technical leaders.

Benefits

Health insurance
Dental insurance
Vision insurance
Long term/short term disability insurance
Employee assistance program
Flexible spending account
Life insurance
Generous time off policies, including; 4-12 weeks fully paid parental leave based on tenure
11 paid holidays
Additional flexible paid vacation and sick leave