Director Post-Si Electrical Validation Engineering

Astera Labs • San Jose, CA

22h

About The Position

Astera Labs is seeking a Director of Post-Si Electrical Validation Engineering to lead development, bring-up, and validation of ASIC SerDes and PCIe PHY products for rack-scale AI infrastructure. The role works across ASIC, systems, firmware, signal integrity, power integrity, mechanical, thermal, manufacturing, and customer engineering teams to guide products from concept and architecture through qualification and mass production.

This is a hands-on leadership role in a fast-moving environment. The director leads and develops an engineering team while contributing to complex technical problem-solving, engaging directly with customers, and improving hardware development processes. The work supports reliable, high-performance connectivity and memory products for cloud service providers, server manufacturers, and networking OEMs.

The role owns ASIC electrical-level (PHY) validation strategy, including validation planning, board and test-fixture development, automation, data review, bring-up, debug, optimization, qualification, and production release. It also leads high-speed SerDes validation and collaborates with internal teams and external vendors to deliver robust, automated, and scalable validation platforms. The position drives products from concept to mass production and improves post-silicon development processes and reusable validation practices.

Requirements

• Bachelor’s degree in Electrical Engineering or a related technical field.
• 12–15+ years of relevant experience, consistent with Astera Labs’ standardized Director level.
• Technical management experience leading design, validation, product, or system engineering teams.
• Experience with high-speed SerDes PHY validation over PVT conditions and taking products from concept through validation planning, validation, production release, and post-production support.
• Strong background in high-speed SerDes IP validation and PHY tuning, signal/power integrity, and automation using common laboratory equipment such as high-speed oscilloscopes, BERTs, and VNAs.
• Entrepreneurial, open-minded behavior and a can-do attitude.
• Strong cross-functional collaboration, technical communication, prioritization, and independent problem-solving skills.

Nice To Haves

• Master’s degree in Electrical Engineering.
• Experience leading SoC debug and development for high-speed interfaces such as PCIe 5, PCIe 6, or PAM4 802.3 Ethernet.
• Working knowledge of high-speed PHY design blocks such as PLLs, DFE, Tx EQ, FFE, and CDR, and signaling concepts such as PAM4.
• Strong Python scripting ability, object-oriented programming knowledge, and basic DevOps experience using Git for source control and collaboration.
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed laboratory equipment such as BERTs, oscilloscopes, and VNAs.
• Startup experience and a proactive, hands-on, customer-focused approach to solving complex problems.

Responsibilities

• Lead ASIC electrical-level (PHY) validation strategy across product definition, architecture, PCB and test-fixture development, validation automation, data review, bring-up, debug, optimization, qualification, and production release.
• Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed ASIC and PHY IP.
• Make hands-on technical contributions to resolve critical design, validation, and customer issues.
• Direct ASIC power-on and bring-up, silicon and PCB debug, PVT characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions.
• Validate high-speed NRZ and PAM4 SerDes-based protocols, including PCIe Gen 3 and above.
• Apply signal- and power-integrity, SerDes/PHY, coding, and laboratory expertise to identify risks and develop practical solutions involving circuits, power distribution, connectors, sockets, and cables.
• Partner with ASIC, system validation, firmware, systems, mechanical, thermal, quality, compliance, manufacturing, and customer engineering teams to deliver robust products.
• Engage internal customers to understand system requirements, evaluate form factors, propose complete board solutions, and resolve issues through production support.
• Collaborate with external vendors for test equipment, bench sockets, temperature forcing units, RF cables, PCB vendors, and related suppliers to ensure validation platforms are automated, robust, and scalable.
• Build, mentor, and develop a high-performing engineering team, establishing clear ownership, technical standards, and execution mechanisms.
• Drive products from concept to mass production, including validation data reviews, code and automation reviews, validation reporting, documentation, and post-production support.
• Improve post-silicon development processes and methodologies, and share lessons learned and validation best practices across Astera Labs’ connectivity and memory product portfolio.

Benefits

• The role may be eligible for discretionary bonus, incentives, and benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Director