Director of Silicon Design for MEM/PCIE COE

Marvell Technology•Santa Clara, CA

13d•$185,390 - $277,700

About The Position

The Center of Excellence (COE), part of the Custom Compute and Storage (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems — spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies — that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle — sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.

Requirements

BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering with 10-15 years of relevant professional experience.
Proven experience delivering complex PCIE/CXL and/or Memory subsystems from architecture through RTL closure
Strong experience in System Verilog RTL development, physical design convergence, power and performance optimization and silicon bring up.
Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
Effective communication and teamwork skills
Mindset for high quality and attention to detail
Independent learner, proactive in problem-solving and finding creative solutions
a good understanding of PCIE/CXL architectures and memory technologies (DDR, LPDDR, HBM).
Proven track record of owning complex subsystems end-to-end across multiple products.
Proven track record of leading distributed, diverse teams across sites.

Responsibilities

Define and scales RTL development, drive reuse across IP and programs
Owns delivery of end-to-end PCIE/CXL and Memory subsystem RTL design execution and sign off
Collaborates with architecture, DV, firmware, SOC and post-silicon teams to influence specifications early and reduce downstream risk.
Manages distributed RTL Design teams, develops technical depth and future leaders.
Accountable for Design schedules, risk assessment, physical design closure, and transparent communication of tape‑out readiness to senior management and key stakeholders
Review and resolve cross-program technical issues and escalations
Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on interoperability and enablement