Director of DV for MEM/PCIE COE
About The Position
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Custom Cloud Solutions Group (CCS) is looking for a DV Technical Director with a demonstrated track record of success in launching products with specific expertise in PCIe and Memory technologies. The person will be responsible for high-quality, predictable delivery of scalable PCIE and Memory subsystems as part of the center of excellence (COE) to all CCS SOC products in 2027 and beyond. A Director of Design Verification for PCIe and Memory must combine deep protocol expertise, system‑level thinking, scalable UVM methodology leadership, and strong people management to ensure A0 silicon production for complex SoCs.
Requirements
- BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering with 10-15 years of relevant professional experience.
- Background in creating test plans and designing test bench architectures that are hierarchical, reusable, and scalable.
- Background in SOC verification and test bench development using UVM and System Verilog, object-oriented programming, and constrained random methods.
- Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
- Effective communication and teamwork skills
- Mindset for high quality and attention to detail
- Independent learner, proactive in problem-solving and finding creative solutions
- a good understanding of PCIE architectures and memory technologies (DDR, LPDDR, HBM).
- proven track record of owning complex subsystems end-to-end across multiple products.
- proven track record of leading distributed, diverse teams across sites.
Responsibilities
- Define and scales UVM‑based verification environments, drive reuse across IP and programs, and ensures comprehensive functional and code coverage.
- Collaborates with architecture, design, firmware, SOC and post-silicon teams to influence specifications early and reduce downstream verification risk.
- Manages globally distributed DV teams, develops technical depth and future leaders.
- Accountable for DV schedules, risk assessment, coverage closure, and transparent communication of tape‑out readiness to senior management and key stakeholders
- Review and resolve cross-program technical issues and escalations
- Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on interoperability and enablement
Benefits
- exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
- offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
- an employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones.
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What This Job Offers
Job Type
Full-time
Career Level
Director
Number of Employees
1,001-5,000 employees
