Director, CRT3 Technology CoE

Celestica International LP•Richardson, TX

3d•Onsite

About The Position

The Director of the CRT3 Technology Center of Excellence (CoE) is an executive-level leadership role responsible for establishing and operating the HPS proof-of-concept (POC) and new product introduction (NPI) lines in Richardson, Texas. The CoE proves new technologies, materials, and processes before transfer to a volume production site. The Director will build and lead the Richardson CoE and bring its two POC lines online in Q1 2027 and two NPI lines online in Q2 2027. The role turns customer and HPS architectures into proven processes through pathfinding and co-development, owns early-build validation on CRT3, and co-validates the technology roadmap well ahead of EVT. The Director works closely with HPS design, Technology Roadmap & Suppliers, MTL and TRL readiness leads, test development, supply chain, and volume sites to ensure transfers include proven process windows and supporting data. HPS NPD integrates functions into a streamlined technical development process without replacing them. The Director leads a 33-role CoE, establishes an engineering culture focused on technical rigor, data-driven decisions, and cross-functional collaboration, and develops on-site expertise in process engineering, tooling, test protocols, and failure analysis. The role manages line allocation and engineering bandwidth across pathfinding sprints, technology qualifications, and NPI builds in alignment with NPD governance priorities. Responsibilities include commissioning and qualifying four Richardson lines in partnership with facilities, CAPEX owners, EHS, IT, and equipment vendors; developing capabilities spanning SMT, back-end assembly, test suites, a failure-analysis lab, and an ISO 6 optics cleanroom; and automating operations using MES, SPC, and station-level traceability. The Director leads pathfinding, technology qualification, and complete NPI launch engagement models, guiding programs through concept intake, DOE execution, rapid prototyping, and process capability optimization. The role also leads Pre-EVT manufacturability pathfinding on decoupled builds with HPS design teams and customer architects. The Director co-validates roadmap technologies, partners with the Director of Technology Roadmap & Suppliers, and hosts supplier and tooling qualification trials. The role owns early-build validation and generates transfer packages containing validated recipes, process windows, and build telemetry for volume sites. It also drives NPD gate reviews and NUDD risk registers to support EVT/DVT first-pass success.

Requirements

12+ years of experience in advanced electronics manufacturing, process development, or NPI within high-performance computing, networking, hyperscaler, advanced semiconductor packaging, or tier-1 EMS environments.
At least 5 years leading engineering teams.
Proven track record specifying, installing, qualifying, and running SMT, back-end, and test lines or a technology development lab, including equipment selection, CAPEX planning, and line qualification.
Deep knowledge of SMT and advanced packaging processes, large BGA and thick-board assembly, thermal solutions, optics, high-speed interconnect, new materials, and solder pastes.
Strong command of DOE, process windows, Cpk, PFMEA, and reliability methods.
Experience with MES, SPC, and traceability systems, and with using build data to drive yield learning and transfer decisions.
Ability to operate effectively in a highly matrixed environment and integrate design, manufacturing, test, supply chain, and site teams.
Proven ability to communicate technology results, line plans, and trade-offs clearly to executives and customer engineering teams.
B.S. or M.S. in Mechanical, Electrical, Industrial, or Systems Engineering.

Nice To Haves

Advanced degree in Mechanical, Electrical, Industrial, or Systems Engineering.
Experience with thermal technologies including cold plates, liquid and two-phase cooling, and TIMs.
Experience in high-performance compute, networking, hyperscaler, advanced semiconductor packaging, or tier-1 EMS environments.

Responsibilities

Lead and scale the 33-role CRT3 Technology CoE, building an engineering culture of technical rigor, data-driven decisions, and cross-functional collaboration.
Develop on-site expertise in process engineering, tooling, test protocols, and failure analysis to de-risk first-of-a-kind materials, equipment, and assemblies.
Manage line allocation and engineering bandwidth across pathfinding sprints, technology qualifications, and NPI builds in alignment with NPD governance priorities.
Commission and qualify two POC lines in Q1 2027 and two NPI lines in Q2 2027, partnering with facilities, CAPEX owners, EHS, IT, and equipment vendors.
Establish line capability across SMT front-end processes, back-end assembly, test suites, a failure-analysis lab, and an ISO 6 cleanroom for optics.
Automate operations using MES, SPC, and station-level traceability.
Lead rapid pathfinding sprints, technology qualifications for new components, and complete NPI launches that prove products before volume handoff.
Guide programs through concept intake, DOE execution, rapid prototyping, and process capability optimization (Cpk).
Lead Pre-EVT manufacturability pathfinding on decoupled builds, partnering with HPS design teams and customer architects to validate concepts on real hardware and freeze designs early.
Co-validate breakthrough technology roadmap items well ahead of EVT and partner with the Director of Technology Roadmap & Suppliers to ensure proving lines address ecosystem needs.
Host supplier and tooling qualification trials.
Own early-build validation on CRT3 lines and create transfer packages with validated recipes, process windows, and build telemetry for volume production sites.
Drive NPD governance through gate reviews and NUDD risk registers to support EVT/DVT first-pass success.
Present technology results, line plans, and trade-offs to executives and customer engineering teams.