Director - AI Enterprise

Axelera AI

4d•Hybrid

About The Position

Axelera AI is seeking an entrepreneurial, technically exceptional engineering leader to establish and run the AI Enterprise Division within the AI Integrated Systems (AIS) group. This new function will focus on taking next-generation accelerator silicon into datacenter-class form factors, including PCIe accelerator cards, OAM-class modules, and full 1U/2U rack systems. The role targets enterprise AI, sovereign cloud, and HPC customers. The successful candidate will be responsible for building the team, defining the technical roadmap, and overseeing the end-to-end delivery of board- and system-level products for two strategic programs. This involves close collaboration with other engineering teams, including Embedded AI, silicon organization, Voyager SDK/software group, and go-to-market teams. The role is deeply hands-on, requiring active involvement in reviewing schematics, layouts, power and thermal budgets, BMC and platform firmware, and lab bring-up.

Requirements

15+ years in hardware engineering for complex electronics products, with at least 5 years in senior leadership roles running multidisciplinary teams.
Proven track record of shipping datacenter- or server-class compute hardware into volume production: accelerator cards, GPU/xPU-class modules, server motherboards, compute nodes or rack-level systems.
Deep expertise in high-speed interfaces (PCIe Gen4/5/6, CXL, high-speed SerDes), enterprise memory, high-current power delivery and VRM design, and high-density PCB layout with rigorous SI/PI methodology.
Experience with BMC-based platform management, Redfish/IPMI, UEFI/BIOS or equivalent firmware stacks, secure boot/root-of-trust, and enterprise RAS features.
Working knowledge of datacenter thermal and mechanical design: air-cooled 1U/2U chassis , direct liquid cooling and/or immersion-ready platforms, and rack power delivery at 12V, 48V and OCP power-shelf level.
Familiarity with datacenter and enterprise compliance (EN 55032/35 Class A, UL 62368, EN 50600, NEBS where relevant) and with OCP standards and contribution/consumption processes.
Experience working with tier-1 CMs/ODMs on server-class products, including DFM, MP transfer, yield ramp and sustaining engineering.
Hands-on ability to review schematics, layouts, simulation results and lab validation data, and to make the call when the team is stuck.
Strong strategic thinker, excellent communicator, skilled at decision-making in fast-moving environments, comfortable engaging at C-level with customers and partners.

Nice To Haves

Experience building or significantly scaling an engineering team is strongly preferred.
Experience with AI accelerator platforms, GPUs or custom silicon in a datacenter context is a strong plus.
Exposure to sovereign AI, EuroHPC, HPC or European defence/dual-use datacenter programmes is a plus.
Fluent English required; additional European language is a plus.

Responsibilities

Build the Enterprise AI Server engineering team from the ground up: hire, structure and mentor a multidisciplinary organisation covering hardware architecture, PCB design, power/thermal/mechanical engineering, firmware and platform validation with in-house and 3rd party resources
Define the technical roadmap for the division’s board- and system-level server products—PCIe Gen5/CXL accelerator cards, OAM-class modules, and full 1U/2U rack systems—aligned with the next-generation silicon roadmap.
Serve as the technical authority across architecture, schematics, PCB stack-ups, high-speed signalling (PCIe Gen5/6, CXL, high-speed SerDes), enterprise memory, power delivery and VRM design, SI/PI methodology, and mechanical/thermal integration.
Own end-to-end execution from concept through design reviews, bring-up, validation, reliability qualification, DFM/DFT/DFR and mass-production readiness, including NPI and ramp with tier-1 CMs and ODMs.
Drive datacenter-grade platform engineering: BMC-based management, Redfish/IPMI, UEFI/BIOS firmware, secure boot and root-of-trust, platform firmware resilience, enterprise RAS features, and out-of-band telemetry.
Lead the thermal and mechanical strategy for high-power accelerator platforms, including air-cooled rack designs and, where appropriate, direct liquid cooling (DLC) and immersion-ready variants.
Ensure compliance with enterprise and datacenter standards: EN 55032/35 Class A, UL 62368, EN 50600 and NEBS where applicable, alongside OCP contribution/consumption where strategic for the division.
Partner with the Embedded AI engineering leadership within AIS to align board- and system-level execution across the two product lines, sharing reference designs, validation assets and CM/ODM relationships wherever it accelerates both streams.
Co-define platform requirements with the silicon, SDK and software teams, memory topology, interconnect fabric, power states, telemetry, so that the server products showcase the accelerator’s capabilities at rack and cluster scale.
Engage directly with strategic customers, system integrators and ecosystem partners (hyperscalers, sovereign cloud operators, HPC centres, OEMs/ODMs) to shape requirements and win design-ins.
Define and enforce engineering processes, documentation standards, validation methodologies and quality gates for the new division, mapped to Axelera’s NPD framework.
Identify and mitigate technical risks, resolve engineering escalations, and drive debugging and root-cause analysis during development, qualification and early production.
Own the division’s engineering budget, CAPEX, external engineering spend and vendor relationships.