Digital Verification Manager

OLIX • Austin, TX

10d • Onsite

About The Position

We’re searching for an ASIC Digital Verification Manager to lead and deliver functional verification of the digital subsystems of our next-generation high-speed mixed-signal ASICs. This is a hands-on leadership role with a strong focus on execution speed, first-silicon success, people management, and cross-functional alignment. You will drive your team to verify complex digital systems that integrate high-bandwidth interfaces, deterministic control loops, and advanced mixed-signal blocks—on schedule, on budget, and with uncompromising quality. As both a leader and technical authority, you will mentor engineers, set a high bar for verification rigor, and ensure the program executes with precision from spec through tape-out sign-off to silicon bring-up and mass production.
This is a rare opportunity to own end-to-end verification leadership on next-generation high-speed mixed-signal ASICs — from architecture through first silicon to mass production — with real authority over strategy, talent, and technical direction. If you thrive at the intersection of rigorous verification discipline and high-stakes execution speed, this role puts you at the centre of the hardest, most consequential problems in modern ASIC development.

Requirements

• 10+ years of digital ASIC verification, with at least 3 full product cycles successfully executed from specification to high-volume production.
• Proven track record of driving on-time, first-silicon success on complex, high-performance ASICs with mixed-signal interfaces (e.g., SerDes, DACs/ADCs, RF SoCs, display/camera pipelines).
• Strong expertise in SystemVerilog/UVM, constrained-random verification, functional coverage, SVA assertions, formal property verification, CDC/RDC sign-off, low-power verification (UPF/CPF), gate-level simulation, and emulation/FPGA prototyping.
• Understanding of mixed-signal verification and ability to partner effectively with analog and design teams on specification splits and verification ownership.
• Demonstrated success in line management and performance management, including hiring, mentoring, and building high-performing verification teams.
• Skilled in fast-paced, cross-functional program leadership with a proven ability to manage schedules, risks, and EDA vendor/tool relationships.
• Outstanding written and verbal communication; confident presenting clear, concise verification status, coverage data, and risk assessments to executives, customers, and cross-site teams.

Responsibilities

• Lead end-to-end verification of digital subsystems (testbench architecture, UVM development, functional and code coverage closure, formal verification, CDC/RDC sign-off, low-power verification, gate-level simulation, and emulation/FPGA prototyping), ensuring aggressive schedule targets are met without compromising quality.
• Define and enforce verification plans, sign-off criteria, and silicon-correlation strategies that catch bugs pre-silicon and drive first-silicon success.
• Manage, mentor, and grow a high-performing, multi-site team of 6–12 verification engineers. Own goal-setting, performance reviews, career development, and hiring across sites, while fostering a culture of accountability, collaboration, and continuous improvement that holds up across time zones.
• Drive seamless collaboration with design, architecture, analog, DFT, firmware, post-silicon validation, and test teams to keep programs moving fast and aligned from spec → vplan → implementation → sign-off → bring-up.
• Define and track aggressive verification schedules, compute and license resource plans, and risk-mitigation strategies. Communicate progress, coverage status, trade-offs, and escalation paths clearly to executives and customers.
• Provide architectural guidance for verification environments targeting high-speed digital subsystems, including multi-lane data paths, clocking and reset schemes, and mixed-signal control loops (real-number modeling and AMS co-simulation).
• Champion verification automation, reusable UVM components, regression and triage infrastructure, streamlined methodologies, and knowledge sharing to deliver high-quality silicon on tight timelines.

Benefits

• Competitive Salary: $388,000+
• Meaningful stock options
• $36k annual Living-Local Bonus if your residence is within 20 minutes of the office
• 33 days of paid time off (PTO), including US federal holidays
• Multiple high-quality medical plan options, including family coverage
• Health Savings Account (HSA) with a high-deductible medical option
• Dental and vision coverage
• Life insurance
• Short- and long-term disability
• Mental health resources
• Fertility and family-building support
• Pre-tax commuter and parking benefits
• 401(k) retirement plan with a 4% employer match
• Access to a dedicated financial advisor
• M4 Macs
• M4 Pro upgrades for engineering team
• High-spec noise-cancelling headphones
• Fully ergonomic workstation
• Access to high-performance 3D printing lab
• Chef-prepared meals (if working late)
• Visa Sponsorship
• Relocation partner provides funding and concierge support

What This Job Offers

• Job Type: Full-time
• Career Level: Manager
• Education Level: No Education Listed