Digital Verification Engineer (MTD, San Jose, CA)
About The Position
Digital functional verification engineers are responsible for the planning, strategy, and execution of challenging FPGA verification projects. This role involves working under the technical supervision of a Verification Lead and requires interfacing with other functional groups such as Hardware, Software, and Applications. Teradyne is a global test and automation specialist, powering next-generation technologies through sophisticated solutions. Our test technology ensures electronic devices work correctly, and our automation solutions help manufacturers develop and deliver products efficiently and cost-effectively. We are committed to attracting, developing, and retaining a high-performance workforce in a positive and inclusive environment, fostering innovation and diversity of thought.
Requirements
- Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 6 years of relevant work experience OR Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 8 years of relevant work experience
- Experience with Verification Test Plan (e.g. Cadence ePlanner)
- Experience with EDA Tools (e.g. Cadence Xcelium, Simvision)
- Experience with System Verilog Constraint Random Testing, Assertions and Functional Coverage
- Experience with UVM Testbench Components development and integration
- Experience with UVM Tests sequences development and testing
- Expertise with Verification IP integration
- Experience with System Verilog/UVM based reference models/Predictors development and integration
- Experience with Industry Standard Protocols (e.g. AXI, PCIe, DDR3/4/5)
- Experience working with revision source control (e.g. clearcase, git, svn)
- Detailed oriented with the ability to bring issues to closure.
Nice To Haves
- Experience in FPGA design implementation with System Verilog
- Experience in verification of Automated Test Equipment functionality
- Experience writing automation scripts (e.g. Make files, shell programming, TCL, Perl, Python)
Responsibilities
- Planning, strategy, and execution of challenging FPGA verification projects.
- Interfacing with other functional groups (e.g., Hardware, Software, Applications).
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Flexible Spending Accounts
- Retirement savings plans
- Life insurance
- Disability insurance
- Paid vacation
- Paid holidays
- Tuition assistance programs
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What This Job Offers
Job Type
Full-time
Career Level
Senior
