Digital Verification Engineer Lead (MTD, Tualatin, OR)

Teradyne•Tualatin, OR

7d•$154,900 - $247,800•Onsite

About The Position

Act as a digital functional verification technical lead responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provide technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. hardware, software, applications).

Requirements

Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 10 years of relevant work experience OR Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 12 years of relevant work experience
Experience with verification planning and testbench architecture
Experience with complete functional verification cycle from Design Specification Review to verification closure
Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification
Expertise with UVM testbench development and Verification IP integration
Experience with Reference models development and integration
Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, AXI, MIPI, DRAM, FLASH
Experience with regression failures analysis
Experience with verification progress tracking
Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
Experience working with revision source control (e.g. clearcase, git, svn)
Ability to track and bring issues to closure. Detailed oriented. Excellent planning and organizational skills.
Experience leading verification team
Experience working with teams located in different time zones
Experience mentoring junior engineers

Nice To Haves

Experience in FPGA design implementation with System Verilog
Experience in verification of Automated Test Equipment functionality
Static and/or dynamic Formal Verification
Experience with GVP source control continuous integration tool

Responsibilities

Planning, strategy, and execution of challenging FPGA verification projects.
Provide technical leadership for large, cross-site verification teams.
Interfacing with other functional groups (e.g. hardware, software, applications).
Verification planning and testbench architecture.
Complete functional verification cycle from Design Specification Review to verification closure.
System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification.
UVM testbench development and Verification IP integration.
Reference models development and integration.
Regression failures analysis.
Verification progress tracking.
Writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python).
Working with revision source control (e.g. clearcase, git, svn).
Track and bring issues to closure.
Leading verification team.
Working with teams located in different time zones.
Mentoring junior engineers.