Digital Verification Engineer

NXP Semiconductors•Austin, TX

About The Position

The Digital Verification Engineer will collaborate with architecture, systems, and design teams to understand product requirements and develop verification plans to meet project specifications. This role is responsible for functional simulations, design debugs, and developing functional (digital) verification plans, test cases, Verification IP, and test bench components. The engineer will also understand development boards and lab equipment to perform digital silicon validation, and develop infrastructure and test cases targeted for an IP, sub-system, or SoC level. Key responsibilities include creating and executing test plans, designing, implementing, and improving UVM test benches, running coverage and regression, analyzing coverage gaps, and devising strategies to achieve higher code coverage. Additionally, the role involves debugging silicon, developing scripts and automation to enhance coverage reports, refining test cases and simulation models, and collaborating with different functional groups to support successful product release.

Requirements

Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, foreign equivalent or related field.
Knowledge gained via completion of a graduate-level course, internship or related occupation involving: Computer Architecture
Digital Integrated Circuit Design
Microprocessor system design
Verilog and System Verilog
Formal verification
Programming language: Python or C/C++
SQL, Jenkins
Data warehouse using Informatica
Troubleshooting and debugging

Responsibilities

Collaborate with architecture, systems and design teams to understand the product requirements and develop verification plans to meet the project specifications.
Responsible for functional simulations and design debugs.
Develop functional (digital) verification plans, test cases, Verification IP, and test bench components.
Understand development boards and lab equipment to perform digital silicon validation.
Develop infrastructure and test cases targeted for an IP, sub-system or SoC level.
Create and execute test plan for the function of design.
Design, implement, and improve UVM test bench.
Run coverage and regression, analyze coverage gaps and devise strategy to achieve higher code coverage.
Debug silicon, develop scripts and automation to enhance coverage reports.
Refine test cases and simulation model.
Collaborate with different functional groups to support successful product release.