DIGITAL VERIFICATION ENGINEER

NXP Semiconductors•Austin, TX

About The Position

This role involves collaborating with architecture, systems, and design teams to understand product requirements and develop verification plans that meet project specifications. The engineer will be responsible for functional simulations, design debugs, and developing functional (digital) verification plans, test cases, Verification IP, and test bench components. The position also requires understanding development boards and lab equipment for digital silicon validation, developing infrastructure and test cases for IP, sub-system, or SoC levels, and creating/executing test plans for design functions. Key activities include designing, implementing, and improving UVM test benches, running coverage and regression, analyzing coverage gaps, and devising strategies for higher code coverage. The role also involves debugging silicon, developing scripts and automation to enhance coverage reports, and refining test cases and simulation models. Collaboration with different functional groups is essential for successful product release.

Requirements

Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, foreign equivalent or related field.
Knowledge gained via completion of a graduate-level course, internship or related occupation involving: Computer Architecture
System-on-a-Chip Design
Digital Circuit and Logic Design
UVM Verification and Formal verification
Testbench
Physical Design Flow
Verilog and System Verilog
Programming language: Python or C/C++.

Responsibilities

Collaborate with architecture, systems and design teams to understand the product requirements and develop verification plans to meet the project specifications.
Responsible for functional simulations and design debugs.
Develop functional (digital) verification plans, test cases, Verification IP, and test bench components.
Understand development boards and lab equipment to perform digital silicon validation.
Develop infrastructure and test cases targeted for an IP, sub-system or SoC level.
Create and execute test plan for the function of design.
Design, implement, and improve UVM test bench.
Run coverage and regression, analyze coverage gaps and devise strategy to achieve higher code coverage.
Debug silicon, develop scripts and automation to enhance coverage reports.
Refine test cases and simulation model.
Collaborate with different functional groups to support successful product release.