Digital Senior Verification Engineer

Ciena Government Solutions • Atlanta, GA

5d

About The Position

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital verification engineer will be required to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products. The digital verification engineer shall read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects. You are held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods. You will contribute to verification planning, functional coverage definition and possibly formal verification test plans. You are accountable for the creation or integration of the test bench environment(s) and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable. You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer. Reporting on status updates on a regular basis

Requirements

• Electrical or computer engineering, computer science or other applicable completed scientific degree at the BEng/BSc, MEng/MSc or higher level
• Proficiency above the intermediate level with the use of System Verilog, UVM, SVA, and simulators from major vendors.
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically address sophisticated technical problems.
• Excellent organization, written and oral (English) interpersonal skills.
• Validated ability in resolving appropriate and comprehensive digital verification and coverage strategies.

Nice To Haves

• Experience with formal verification methods
• Experience with standards and protocols such as OTN/FlexO/B100G, Ethernet (100GE+)
• Experience with using GIT for source code management and revision tracking
• Experience with using Jira for schedule planning, assignment tracking and bug reporting
• Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, System C

Responsibilities

• Propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.
• Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
• Complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods.
• Contribute to verification planning, functional coverage definition and possibly formal verification test plans.
• Creation or integration of the test bench environment(s) and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.
• Perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer.
• Reporting on status updates on a regular basis

Benefits

• Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.
• We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
• At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.
• Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
• Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
• If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 1,001-5,000 employees