Senior Verification Engineer

Analog Devices•Wilmington, MA

11d•$110,385 - $151,808•Onsite

About The Position

Analog Devices is seeking a highly motivated Senior Design Verification Engineer to join our Security IP team developing next-generation hardware security solutions. Our technology integrates embedded processors, hardware cryptographic accelerators, secure memory architectures, and security-focused peripherals to provide foundational hardware security capabilities across ADI products. In this role, you will own verification efforts for complex security IP and subsystem designs, working closely with design, architecture, firmware, and validation teams to ensure robust functionality, security, and quality. You will develop advanced verification environments, drive coverage closure, debug complex failures, and contribute to reusable verification methodologies used across multiple security products.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Typically 4–7 years of experience in digital design verification.
Strong proficiency in System Verilog and UVM methodology.
Experience developing reusable verification environments, scoreboards, checkers, and coverage models.
Strong understanding of verification concepts including: Constrained-random verification, Functional coverage, Assertion-Based Verification (SVA), Regression management, Coverage closure.
Experience with RTL simulation and debug tools (e.g., VCS, Xcelium, Simvision, Verdi, Questa).
Strong analytical and debugging skills with demonstrated ability to independently solve complex verification challenges.
Experience with scripting languages such as Python, Perl, or Tcl.
Experience doing System on Chip (SoC) verification involving writing C test cases.
Experience working in Linux environments
Experience verifying processor-based systems such as ARM Cortex-M, RISC-V, or similar embedded processors.
Experience with common SoC interfaces such as APB, AHB, AXI, QSPI, UART, and DMA architectures.

Nice To Haves

Experience verifying hardware security IPs including AES, SHA-2/SHA-3, RSA, ECC, Post-Quantum Cryptography accelerators, Key management and secure storage blocks
Familiarity with secure enclave architectures, Root of Trust implementations, secure boot flows, DICE attestation, or trusted execution environments.
Understanding of hardware security concepts including: Authentication, Secure provisioning, Access control, Key protection, Fault injection resistance, Side-channel attack mitigation.
Experience using formal verification tools and methodologies.
Experience with emulation platforms and firmware/software-driven verification.
Familiarity with AI-assisted engineering tools and verification productivity workflows.

Responsibilities

Own block-level and subsystem-level verification activities for security-focused IPs and secure enclave solutions.
Develop comprehensive verification plans based on architecture specifications, threat models, and product requirements.
Create, enhance, and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, assertions, and functional coverage models.
Develop constrained-random and directed test scenarios targeting functional, security, and corner-case behaviors.
Drive verification closure through code coverage, functional coverage, assertion coverage, and regression analysis.
Collaborate with RTL designers, architects, firmware engineers, and security experts to understand design intent and security requirements.
Debug complex RTL and simulation failures, perform root-cause analysis, and drive issue resolution.
Verify processor-based subsystems writing C tests, hardware cryptographic accelerators, secure boot mechanisms, key management functions, and security controllers.
Support emulation, firmware integration, and post-silicon validation activities.
Contribute to reusable VIP, automation infrastructure, and verification methodology improvements across the organization.
Mentor junior verification engineers and provide technical guidance on verification best practices.