Digital Mixed Signal Modeling Engineer

Apple • Austin, TX

8h • Onsite

About The Position

Join Apple's team to develop mixed-signal PMU ASICs for Apple's hardware products. PMUs include mixed-signal functions like throttling, system telemetry, and high-performance power conversion blocks (buck converters, LDOs, charge pumps, voltage references) crucial for industry-leading battery life. As a member of the mixed-signal ASIC team, you will design, develop, and validate SystemVerilog real-number models of complex analog IPs that interface with digital control blocks. These models are essential for closing the loop in digital mixed-signal simulations, helping to identify bugs in both digital and analog design portions before silicon production. The PMU Digital Mixed Signal (DMS) team offers a unique opportunity bridging digital and analog design. DMS engineers collaborate closely with analog and digital designers to create SystemVerilog real-number models (RNM) of analog circuits, capturing key behaviors such as DC-DC converter regulation, overshoot/undershoot, and ripples. These models enable high-speed digital/analog closed-loop simulations, running over 100x faster than schematic-based simulations, providing significant productivity gains. DMS simulations have been fundamental to the PMU team's success in meeting aggressive schedules and delivering leading power converters. You will work at the intersection of analog and digital design, involving reading schematics, attending architecture and design reviews, building and debugging models, and correlating results against transistor-level simulations. This role provides deep exposure to full-chip integration, tapeout cycles, and silicon bring-up correlation across Apple's product portfolio.

Requirements

• A minimum of a bachelor's degree in relevant field
• A minimum of 3 years of relevant industry experience

Nice To Haves

• Solid understanding of both digital and analog circuit fundamentals
• Proficiency in Verilog or SystemVerilog
• Ability to read and interpret analog schematics and simulation results
• Excellent communication and cross-functional collaboration skills
• Experience with SystemVerilog real-number modeling (RNM) or wreal/EEnet methodology
• Hands-on experience with power management circuits such as LDOs, buck converters, charge pumps, or voltage references
• Familiarity with digital verification methodology (e.g., UVM, coverage-driven verification)
• Experience with mixed-signal or digital simulation tools (e.g., Xcelium, Virtuoso)
• Proficiency in Python or similar scripting for automation and analysis
• Experience using LLM-based or AI-assisted coding tools for model or RTL development

Responsibilities

• Design, develop, and validate SystemVerilog real-number models of complex analog IPs that interface with digital control blocks
• Capture key behaviors such as DC-DC converter regulation, overshoot/undershoot and ripples in models
• Work closely with analog and digital designers
• Read and interpret analog schematics
• Attend architecture and design reviews
• Build and debug models
• Correlate results against transistor-level simulations

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees