Senior Digital Mixed-Signal (DMS) Verification Engineer
About The Position
Join Broadcom, a global technology leader and Fortune 500 powerhouse at the forefront of semiconductor innovation and AI infrastructure. Within our specialized Mixed-Signal ASIC division, we build the critical IP that drives next-generation enterprise storage solutions. We are looking for a Senior DMS Verification Engineer to act as a localized methodology leader and key technical bridge for our worldwide engineering organization. This unique opportunity allows a verification architect to drive quality initiatives, pioneer modern automation (including AI-assisted workflows), and establish robust methodologies across our US and Asia design centers.
Requirements
- Experience: 5+ years of hands-on experience in digital verification of mixed-signal ASICs or SoCs.
- Verification Methodology: Deep expertise in coverage-driven verification processes and frameworks (UVM/OVM).
- Analog/Digital Boundary Expertise: A strong understanding of event-driven simulator-based modeling techniques and how digital logic interacts with analog boundaries.
- Leadership: Proven ability to coordinate technical problem-solving across cross-site and global teams. Excellent English communication skills to translate product definitions into executable plans.
- Education: Bachelors in Electrical Engineering, Computer Engineering, or Computer Science and 8+ years of related experience or Masters degree in Engineering and 6+ years of related experience
Nice To Haves
- Mixed-signal ASIC UVM / OVM experience preferred.
- Hands-on experience with SystemVerilog Assertions (SVA) and behavioral modeling of analog circuits.
- Proficiency in scripting to automate verification workflows, manage regressions, and streamline simulation infrastructure.
Responsibilities
- Testbench Architecture: Architect, develop, and maintain advanced UVM-based testbenches for the functional verification of complex mixed-signal ASIC products.
- Methodology Leadership: Champion verification quality by integrating new methodologies, such as SystemVerilog Assertions (SVA) and UVM/OVM, to reduce mixed-signal validation bottlenecks.
- Global Team Liaison: Act as the primary liaison between our local US digital design teams and our worldwide verification teams, translating complex specifications into seamless execution.
- Flow Automation: Lead initiatives to explore and integrate modern automation and AI-assisted verification workflows to accelerate testbench generation and debug efficiency.
- Tape-out Execution: Own verification efforts at both the block and system levels for major tape-out projects, driving functional and code coverage to closure.
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Number of Employees
5,001-10,000 employees
