Staff Digital IC Design Engineer

Marvell Technology • Ottawa, ON

3d • CA$98,100 - CA$130,800

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. The Connectivity BU develops cutting-edge optical Ethernet Transceiver ASICs. The latest datacenter architectures need to scale rapidly for widescale AI adoption. In order to respond to the dramatically increased demands of cloud-based connection capability, major hyperscalers urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs. As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams and timing closure. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
• 5+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology.
• Familiarity with the entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
• Experience with Verilog, System Verilog, Python, and Unix Shell.
• Experience in both RTL development (block and subsystem level) and gate level verification and debug.
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
• Effective communication and presentation skills and a team player

Responsibilities

• Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
• Develop high speed data path and control plane RTL blocks using Verilog, synthesis and backend resources
• Integrate vendor IP and support
• Well versed with the complete ASIC flow from micro-architecture to customer deployment
• Post-silicon debug and correlation
• Develop ASIC specification and micro-architecture of signal processing and communications algorithms
• Assist in design automation of various aspects of the CAD EDA flow.

Benefits

• competitive compensation
• great benefits
• workstyle within an environment of shared collaboration, transparency, and inclusivity
• tools and resources they need to succeed in doing work that matters, and to grow and develop with us

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level