Digital Design Verification, Principal Engineer / Architect-17853

Synopsys•Austin, TX

130d•$166,000 - $249,000•Onsite

About The Position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You are a visionary and highly experienced engineering professional, passionate about verification and digital design methodologies. With at least 5 to 10 years of solid experience in IP and SoC verification, you have consistently demonstrated technical excellence and leadership in your career. You thrive in challenging environments and are adept at architecting robust verification infrastructures from the ground up, particularly within the EDA ecosystem.

Requirements

Minimum 12+ years of hands-on experience in IP/SoC verification, with a proven track record of hands-on technical contributions.
Good understanding of Agentic AI technologies specifically Cursor and/or VS Code co-pilot.
Passion to learn Agentic AI mechanisms and apply them for design verification.
Familiarity with Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
Demonstrated ability to validate verification flows and infrastructure for complex digital designs.
Solid programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar languages).
Bachelor’s or Master’s degree in electrical/Electronics/Computer engineering
Experience with multi-tasking and managing technical projects independently.
Ability to document, communicate, and propagate technical methodologies across global teams.

Nice To Haves

Exposure to Agentic AI EDA tools will be a big plus.

Responsibilities

Applying AI techniques to accelerate design verification – leveraging internal and/or external agentic AI tools to generate verification plan, testcases, coverage and debug collaterals
Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.
Partnering with global engineering teams to define, document, and propagate best-in-class verification methodologies and standards.
Leading and mentoring junior engineers, fostering a culture of technical growth, innovation, and collaboration within the team.
Driving technical initiatives and independently managing high-impact assignments, ensuring timely and high-quality deliverables.
Collaborating closely with tool development teams to influence product evolution and optimize verification workflows for maximum efficiency.
Supporting customers and internal stakeholders by troubleshooting, optimizing, and refining verification processes and flows.